| Placemen t and routing heuristics for a Field Programmable Multi-Chip Module (FPMCM) are presented. The placement is done in three phases; partitioning, chip assignment and iterative improvement. The routing is done in two phases; global routing followed by detailed routing. Detailed routing involves new channel routing problems denoted by Exact Segmented Channel Routing (ESCR) and K-ESCR. A very fast K-ESCR heuristic is described. Experimental results show that the placement heuristic achieves high gate utilization, and that the K-ESCR heuristic performs surprisingly well over wide range of channel sizes.
The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size.
But the design of an MCM system usually requires weeks of engineering effort, thus
we need a generic MCM substrate with programmable interconnections to accelerate
system prototyping. In this paper, we propose a Symmetric and Programmable MCM
(SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical
array of slots for bare-chip attachment and Field Programmable Interconnect Chips
(FPICs) for substrate routing. Experimental results demonstrate that our FPIC polygonal
routing module uses 12% less switches than the conventional routing module
for interconnecting bare-chip slots with 84 pads. Also, experiments are conducted to
determinate proper parameters for the VLSI implementation of our FPIC.
The programmable routing network of Field Programmable Gate Array (FPGA) and Field Programmable Interconnection Chip @TIC) affects its performance, die size, and routability. This paper proposes a polygonal routing network that consists of polygonal switch modules and many rectangular connection modules. For a logic module with 2n pins, the number of switches used in the polygonal routing module is less than the conventional routing module by O(&).
To accelerate prototyping designs, we propose a new Symmetric and Programmable MCM (SPMCM) substrate, which consists of 'a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Especially, the FPIC that we developed contains two kinds of polygonal routing modules and some virtual-wires to reduce the number of routing switches and pin count. For a bare-chip slot with 2n pads, the number of switches used in the polygonal routing module is less than the conventional routing module by m J 4 times, where the flexibility ratio T F~ is close to 1. 0-7803-5650-0/99/$10.00 0 1999 IEEE
ÐThis paper proposes a three-stage rearrangeable polygonal switching network (PSN) for interconnecting one-sided input-output terminals. In comparing our PSN with a three-stage one-sided Clos switching network of the same size and with the same number of switches, we prove that rearrangeability of a PSN is better than that of a Clos switching network. Also, the switches efficiency of PSN is explored.
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