A 10 bit 40 MHz ADC using 0.8 mu m Bi-CMOS technology

Tsugaru, Kazunori; Sugimoto, Yasuhiro; Noda, Makoto; Sasaki, Gen; Suwa, Yoshito

doi:10.1109/bipol.1989.69458

Proceedings of the Bipolar Circuits and Technology Meeting

DOI: 10.1109/bipol.1989.69458

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A 10 bit 40 MHz ADC using 0.8 mu m Bi-CMOS technology

Kazunori Tsugaru

Yasuhiro Sugimoto

Makoto Noda

et al.

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A 12-b 5-Msample/s two-step CMOS A/D converter

Razavi

Wooley²

1992

IEEE J. Solid-State Circuits

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Two-step flash architectures are an effective means of realizing high-speed, high-resolution analog-to-digital converters (ADC'S) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. This paper describes the design of a 12-b, 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a l-pm CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm x 3.7 mm.

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A 12-b 5-Msample/s two-step CMOS A/D converter

Razavi

Wooley²

1992

IEEE J. Solid-State Circuits

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A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

Ohhata¹,

Wataru²,

Tabira³

et al. 2014

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A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.

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A 10 bit 40 MHz ADC using 0.8 mu m Bi-CMOS technology

Cited by 2 publications

References 3 publications

A 12-b 5-Msample/s two-step CMOS A/D converter

A 12-b 5-Msample/s two-step CMOS A/D converter

A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

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