A 40‐Msps 10‐bit video A/D converter LSI has been developed. A 0.8‐μm BiCMOS technology is applied. The two‐step parallel type conversion scheme is adopted, using the MOS analog switch and bipolar comparator. A redundant structure is employed using 5 bits for the coarse stage and 5.5 bits for the fine stage. Three points of voltages in the coarse ladder circuit are transferred to the fine ladder resistor circuit and are used as the upper‐end, middle‐point and lower‐end voltages.
Wire connection configuration for the fine ladder resistors is redesigned so that the error is reduced and the speed is improved. A high‐speed circuit with a preamplifier is used in the fine comparator. Protection functions for the overflow and underflow are also provided. With this design, the S/N ratio of 60 dB is realized, for the clock frequency of 40 MHz and the full‐scale 50‐kHz input. The designed LSI operates with the 5‐V single supply. Power consumption is 700 mW, the number of elements is 7000, and the chip size is 4.1 × 4.8 mm2. The following performance is obtained by overall evaluation of the printed board containing the S&H IC and DAC. The D.G. and D.P. for 40‐MHz clock are 1 percent and 1 deg, respectively. The S/N ratio is 52 dB for 10 MHz full‐scale input and 48 dB for 20‐MHz full‐scale input. A future problem involves the on‐chip implementation of the S&H circuit.
A +5-V single-power-supply 10-b video BiCMOS sampleand-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation has been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2-pm BiCMOS technology and evaluated. The following results have been obtained 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-11s acquisition time at 1-V step input, 15-11s switching settling time, and 0.1% linearity error. Power dissipation is 150 mW.
This paper discusses the sample‐and‐hold IC to be placed in front of the 10‐bit serial‐parallel analog/digital converter (ADC). The realization of an IC in operation with a +5‐V single supply is discussed, considering the integration with ADC and the system‐on‐chip implementation in the future. The buffer circuit with a configuration based on NPN and PNP complementary elements is employed. The combination of PMOS and NPN elements is newly devised and applied, as a way to realize the high‐speed PNP element.
Applying 1.2‐μm BiCMOS process to this circuit, IC is constructed and evaluated. As a result, the performances of maximum operating frequency 40 MHz, the signal‐to‐noise ratio of 63 dB for the 8‐MHz full‐scale signal input, the acquisition time of 20 ns for 1‐V step input, D.G. of less than 1 percent and D.P. of less than 0.5° are obtained. Thus, the sample‐and‐hold IC with the single voltage supply and 10‐bit accuracy is realized.
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