Oversampled analog-to-digital (A D) converter architectures offer a means of exchanging resolution in time for that in amplitude so as to avoid the difficulty of implementing complex precision analog circuits. These architectures thus represent an attractive approach to implementing precision A/D converters in scaled digital VLSI technologies. This paper examines the practical design criteria for implementing oversampled converters based on second-order sigma-delta (ZA) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order 2 A modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3-pm CMOS technology. This experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 m d , and achieved a measured dynamic range of 89 dB.

No abstract

No abstract

This paper describes precision techniques for the design of comparators used in high-performance analog-to-digita1 converters employing parallel conversion stages. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 pV at a IO-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 pV at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW.

No abstract