A 1.8GHz Digital PLL in 65nm CMOS

A 2GHz Digital PLL, with temperature lock range of −40°C to 125°C, in 45nm CMOS

“…The Digitally Controlled Oscillator (DCO) in a Digital PLL (DPLL) can be either LC-tank based [1][2][3], or ringoscillator based [4][5][6][7][8]. In applications where close-in phase noise is not critical, ring-oscillator DCOs may be preferred.…”

“…This is because LC DCOs are more difficult to design, have a limited frequency range, occupy more silicon area, and are susceptible to inductive noise pick up in the presence of multiple PLLs, or on noisy digital chips. In a ring-oscillator based DCO, it is typical to have separate Coarse and Fine controls [4][5][6][7][8], with the Coarse control, calibrated at power up, providing most of the DCO range, and the Fine control providing the required resolution while the DPLL is in lock. ΣΔ operation can be used on the Fine control to get better frequency accuracy with fewer controlling elements [4] [6][7][8].…”

“…Ring oscillator based DCOs, however, show a large temperature dependence, and additional corrections may be required to keep the DCO in the range of the Fine control [4][5] [7] [8]. Any such correction causes a frequency error at the DPLL output for a finite time based on the DPLL bandwidth [4].…”

“…Ref. [4] and [8] use a Very Low Pass Filter (VLPF) to apply corrections for temperature gradually, so that the frequency error at the DPLL output may be minimized. This approach is not scalable: as technology shrinks and capacitor leakages increase, the VLPF becomes difficult to design.…”

“…This approach is not scalable: as technology shrinks and capacitor leakages increase, the VLPF becomes difficult to design. For the 45nm process used in this work, and for a design similar to that used in [4] and [8] the voltage drop across the VLPF would have been several 10s of mV causing significant error. In [7], a double integral path and an additional Compensation ΣΔ DAC are used to extend the range of the DCO.…”