A 2GHz Digital PLL, with temperature lock range of −40°C to 125°C, in 45nm CMOS

Abstract

A 2GHz, ring-oscillator based Digital PLL (DPLL) with temperature lock range of -40°C to 125°C is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range and hence the DPLL temperature lock range, even as the ΣΔ step size and range are kept small to minimize jitter. The DPLL achieves a phase noise of -90dBC/Hz at 1MHz offset for 2GHz operation. It supports an input frequency range of 0.5MHz to 50MHz, occupies a core area of 0.09mm 2 and consumes 7.2mW.