A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor

Sukegawa, S.; Umebayashi, Taku; Nakajima, Tasuku; Kawanobe, H.; Koseki, K.; Hirota, Isao; Tsutomu, Haruta; Kasai, M.; Fukumoto, K.; Wakano, T.; Inoue, Ken; Takahashi, Hideki; Nagano, Takashi; Nitta, Yoshikazu; Hirayama, Teruo; Fukushima, N.

doi:10.1109/isscc.2013.6487825

Cited by 141 publications

(39 citation statements)

References 4 publications

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“…Finally, conclusions are drawn in Section V. Fig. 1(b) shows the proposed imager architecture in a dual tier stacked technology: the top silicon layer (tier 0) implements the 4T-pixels array based on the mainstream backsideilluminated [11] technology, while the second layer (tier 1) implements the readout circuitry. By using BSI at the top, the two tiers can be face-to-face connected through micro-bumps [12], avoiding the need for Through-Silicon-Vias (TSV).…”

Section: Introductionmentioning

confidence: 99%

“…This is a powerful feature as it allows the technology scaling of the second tier, without impacting the optical performance, potentially increasing the digital I/O speed and reducing the power consumption of the digital blocks. b) Decreased imager chip area: Placing the readout circuitry at the bottom tier instead of laterally to the pixel array decreases the total footprint [11]. c) Parallel readout: Each bump can connect a sub-array of pixels of tier 0 to its own readout block at tier 1, allowing a parallel readout which can be kept constant at variable resolutions.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

2014

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The continuously increasing array resolution of CMOS imagers poses a great challenge in combining highframe-rate and low light detection in the same sensor. To cope with this, parallel readout architectures are needed. This paper proposes a readout architecture for 8K stacked image sensors, which uses a novel 1D decoding readout based on block-of-pixels and incremental-sigma-delta ADCs. The proposed 1D decoding system reduces the control lines of the pixels and allows a simpler decoding, an increased parallelism, and an improved robustness over process yield. The experimental results from a test chip implemented in a standard CIS technology show that at 10 μm pixel pitch, the proposed readout architecture can achieve a highframe-rate of 730 frames/s and a low read noise of 1.4 e − . In a real stacked implementation, the frame rate can further increase to about 960 frames/s at 8K resolution, at the cost of a slight increase in thermal noise by 14 μV.Index Terms-Image sensor, UHDTV, dynamic range, low noise, high frame rate, 3-D integration, stacked, high resolution, ADC, incremental .

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

2014

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“…10 shows a back-illuminated stacked CIS (stacked BI-CIS) where a very thin BI-CIS chip is stacked on a logic chip. CuTSVs with different depths are used in this stacked BI-CIS [35,36]. A 3D-stacked CIS with more layers is expected for the automobile application.…”

Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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“…(1,2) Despite these advantages, difficulties arise in pixel design owing to the scaling down of the CMOS process. (3) In the conventional CIS, the active-pixel sensor (APS) is based on a p-n junction photodetector. However, many types of photodetectors have been developed for image sensors, including the bipolar junction transistor (BJT), hole accumulation diodes (HADs), silicon-on-insulator (SOI), and avalanche photodiode (APD).…”

Section: Introductionmentioning

confidence: 99%

Complementary Metal Oxide Semiconductor Image Sensor Using a Gate/Body-Tied P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector for High-Speed Binary Operation

2018

Sensors and Materials

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In this paper, we propose a CMOS image sensor that uses a gate/body-tied p-chnnel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector for highspeed binary operation. The sensitivity of the gate/body-tied PMOSFET-type photodetector is approximately six times that of the p-n junction photodetector for the same area. Thus, an active pixel sensor with a highly sensitive gate/body-tied PMOSFET-type photodetector is more appropriate for high-speed binary operation. Moreover, the CMOS image sensor for binary operation has the advantages of low power consumption and a simple circuit because an analogto-digital converter is not necessary. The proposed image sensor was fabricated and measured using a CMOS 0.35 μm conventional process.

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A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor

Cited by 141 publications

References 4 publications

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

Recent progress in 3D integration technology

Complementary Metal Oxide Semiconductor Image Sensor Using a Gate/Body-Tied P-Channel Metal Oxide Semiconductor Field Effect Transistor-Type Photodetector for High-Speed Binary Operation

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