Recent progress in 3D integration technology

With continuous increase in the off-chip bandwidth requirements, conventional interconnection methodologies are quickly becoming incapable of meeting the demand. Recent progress in silicon interposer and 3D integration technologies seek to alleviate some of these bottlenecks. This paper reviews the evolution of conventional interconnect methodologies and recent progress in platforms allowing high-bandwidth low-energy chip-tochip communication.

Section: Emerging Methodologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

“…Through Silicon Via (TSV) provides a promising way to achieve low latency and low power interdie connection and has gained considerable attention in threedimensional (3D) integration [1,2]. However, the yield of TSV-based 3D integrated circuits (ICs) is unsatisfactory in the semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

An effective structure and flow for pre-bond TSV test

Pei

Song

2018

Pre-bond TSV test plays a vital role in improving the yield and reducing the cost of 3D ICs. In this paper, we proposed an effective test structure and flow for pre-bond TSV test. In the test structure, the resistorcapacitor parameter related to a specific TSV can be reflected by oscillations with high accuracy. By analyzing the period variations between two oscillations generated in successive test steps, the proposed test scheme enables quick detection of faulty TSVs. Experimental results have demonstrated the effectiveness of the proposed pre-bond TSV test scheme.

“…In traditional 2D processor, more circuits means larger area and longer wires, but the limit of long wire delay has been seem as an unsolved challenge [2]. To keep improving the performance of microprocessors and extend the capabilities of a single processor, three-dimensional integrated circuits (3D IC) is proposed [3].…”

Section: Introductionmentioning

confidence: 99%

Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system

Guo

Zhang

Yao

et al. 2016

Multi-core 3D IC is a new solution for greater quantity of cores, but with critical challenge of internal thermal. The interlayer cooling system is introduced for this problem, and expends the design space of task allocation. This work proposes a thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system, integrated with simulated annealing method. The results show that the maximal temperature and temperature gradient reduced by 19.4°C and 5.1°C respectively, compared to the randomized policy, and obtain better balance between normal and extreme cases than traditional ranking policy, in a design of 3 active device layers.