A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

Abstract

Mobile DRAM is widely employed in portable electronic devices due to its feature of low power consumption. Recently, as the market trend renders integration of various features in one chip, mobile DRAM is required to have not only low power consumption but also high capacity and high speed. To attain these goals in mobile DRAM, we designed a 1Gb single data rate (SDR) Wide-I/O mobile SDRAM with 4 channels and 512 DQ pins, featuring 12.8GB/s data bandwidth. Figure 28.5.1 shows the chip architecture with 4-channels and 16 segmented 64Mb arrays. The whole chip is made up of 4 partitions which are symmetric with respect to the chip center, and each partition consists of 4×64Mb arrays, peripheral circuits and microbumps. Each channel has its own input pins while external power pins and internal voltage generators are shared with the other channels. In a single channel, 128 data lines are controlled to feed 128 DQs. Four 64Mb arrays in 1-channel can be configured in 4 banks with bank addresses BA [0:1] and row addresses RA [0:11], or in 2 banks with BA [0] and RA [0:12]. In a 4-bank structure, each bank has 4k row depth and 8k page depth.To reduce power consumption in 512b I/O operations and to support high data bandwidth, I/O driver loading is reduced by adoption of 44×6 microbump pads per channel, which are located in the middle of the chip. Figure 28.5.1 also shows a SEM image of the fabricated microbumps with 20×17μm 2 size and max 50μm pitch. To detect bump connection failure with other devices, a simple boundary scan test mode is implemented. It is a subset of IEEE Standard 1149.1 [1] in pin configurations and in operational modes to reduce chip size burden. Each channel has its own scan chain and scan clock input. To reduce the number of ballouts, this mode scans parallel data I/O and the scanned data propagates through the dedicated pins. Normal device operation is performed after the boundary scan test is finished. Figure 28.5.2 shows boundary scan block and AC timing diagram. This boundary scan chain is enabled when /SEN, scan enable pin, is low. The data input from the pad is captured when /SSH, scan shift pin, is low, and it is shifted along the chain when /SSH is high. SDI, SDO and SCK pins are for scan input, output and clock, respectively.We also adopt typical metal pads for test purposes since it is difficult to probe small microbumps directly. These pads are aligned in vertical direction at the chip center to allow precise correlation with microbumps and to reduce skews between channels. With test pads, this DRAM is handled as SDR×16, but internally as SDR×128 per channel. Selections of 16 out of 512 data can be done with column addresses, which are for the read-out of result data through test pads. Figure 28.5.3 shows correlation scheme between microbumps and test pads in data write/read operations. Through test pads, 9.3ns delayed outputs of microbumps, 2ns for clock propagation from pad and 7.3ns for data transfer from microbump to pad, are measured. Because we redirect outputs from microbumps and i...

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