A 1.29 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.12 um spacer-on-stopper (SOS) CMOS technology

The effects of gate notching profile defect on transistor performance in cell NMOSFETs of lowpower SF2AM device with 0.12 pm channel length were investigated. Experimentally it could be found that the gate notching profile defect causes the serious degradation of the transconductance and the transistor drive current. In the simulation using TSUPREM4, we could manifest that the degradation of transistor characteristic is owing to the penetration of the gate notching into the channel region over the sourceldrain (S/D) extension region and the rapid reduction of gate electric field. And, it was also found that the degradation of the transistor performance is more sensitive to the notch depth rather than the notch height.

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A 1.29 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.12 um spacer-on-stopper (SOS) CMOS technology

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References 1 publication

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

Effects of gate notching profile defect on characteristic of cell NMOSFET in low-power SRAM device

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