A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Song, Keunsoo; Lee, Sang Kwon; Kim, Dongkyun; Shim, Young Bo; Park, Sang-Il; Ko, Bokrim; Hong, Duckhwa; Joo, Yong-Suk; Lee, Wooyoung; Cho, Yongdeok; Shin, Woo Young; Yun, Jaewoong; Lee, Hyengouk; Lee, Jeonghun; Lee, Eunryeong; Yang, Jin Kyu; Jung, Hae-Kang; Jang, Namkyu; Cho, Joohwan; Kim, Hyeongon

doi:10.1109/cicc.2014.6946032

Cited by 4 publications

(1 citation statement)

References 1 publication

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“…The diversity of high-speed I/O standards for DRAM requires an automated way of doing production tests over a variety of channels [1,2,3,4,5,6,7]. DRAM standards, such as DDR4, LPDDR4, GDDR5, and HBM address different application-specific needs in PCs, mobile devices, graphics processors, and artificial intelligence (AI) accelerators, respectively [8,9,10,11], and use different I/O channels whose loss characteristics span a wide variety, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Kim

2019

IEICE Electron. Express

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This paper describes a transmitter that can emulate a wide variety of frequency-dependent loss characteristics of high-speed dynamic random-access memory (DRAM) channels, with an aim to facilitate an automated test procedure for a DRAM interface, which does not require physical reconfiguration of channels. Specifically, the proposed transmitter can generate the waveform of an NRZ data stream that has experienced adjustable amounts of skin-effect loss and dielectric loss in electrical channels. To save the hardware cost of implementing a high-speed, high-resolution digital-to-analog converter, the transmitter constructs the waveform using a set of logarithmic and exponential basis functions, each of which is implemented using a pseudo-logarithmic amplifier and lowbandwidth amplifier with adjustable gain and bandwidth, respectively. The prototype chip, fabricated in a 65-nm CMOS process, occupies an area of 5200 µm 2 and operates over 1.4-7 Gbps while dissipating 38 mW at 7 Gbps. It is demonstrated that the implemented transmitter can emulate 10-40"-long microstrip lines on an FR4 grade material with a peak error less than 12.5% in the pulse response.

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Section: Introductionmentioning

confidence: 99%

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Kim

2019

IEICE Electron. Express

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Neural-Network Based Functional Evaluation on Thermograms of Wireless Circuits

Sultan

Yassin

Farouk

2017

Proceedings of the International Conference on Advanced Intelligent Systems and Informatics 2017

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A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel

Lee

Song

Byeon

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier channel. A BER that is less than 1e-12 is achieved in 65nm CMOS. The power efficiency of the transceiver is 5.9pJ/bit with 120Ω terminations at each transceiver side.

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A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Cited by 4 publications

References 1 publication

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Neural-Network Based Functional Evaluation on Thermograms of Wireless Circuits

A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel

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