A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Nambu, H.; Kanetani, K.; Idei, Y.; Masuda, Takatsugu; Higeta, K.; Ohayashi, M.; Usami, M.; Yamaguchi, K.; Kikuchi, Toshiyuki; Ikeda, Takahide; Ohhata, Kenichi; Kusunoki, T.; Homma, N.

doi:10.1109/4.375971

Cited by 12 publications

(5 citation statements)

References 31 publications

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“…The SRAM macro shown in this paper achieves an access time of 125 ps at a working frequency of 4 GHz with a −3.4 V power supply using IBM 8HP technology, which is shorter compared with the designs using other technologies. The power–delay product is much lower than the power–delay product of 2145 ps W for the design using 0.2 μm BiCMOS presented in paper [23] and 6300 ps W for the design using 0.3 μm BiCMOS presented in paper [39]. Compared with the implementation in [36] using 45 nm CMOS technology with access time of 450 ps, this macro implemented in 8XP achieves much shorter access time (125 ps) with a reasonable power consumption of 0.73 W and a power–delay product of 91 ps W. Compared with the implementation in [37] using 100 nm CMOS, this macro designed in 8XP and 8HP achieves shorter access time with less area consumption.…”

Section: Test and Measured Resultsmentioning

confidence: 98%

“…The area and power density of this macro is smaller than the density of the former 0.2 μm BiCMOS SRAM implementation [23]. Compared with the 130 nm CMOS [38] implementation, the area density of this macro is around 5 times larger, whereas the access time of this macro is 5 times less.…”

Section: Test and Measured Resultsmentioning

confidence: 99%

“…The BiCMOS technology is used to design this SRAM macro because it can combine CMOS memory's high density and low power characteristics with bipolar memory's high‐speed advantage, which leads to a promising way to meet the L1 cache requirement in a ultra‐high‐speed BiCMOS microprocessor [15–17]. Several high speed, 0.65–1.5 ns, high density, 64‐kb–1.15‐Mb, emitter‐coupled logic (ECL)‐CMOS SRAMs have been fabricated using an ECL‐CMOS SRAM circuit technique [18–25] that lay a solid foundation for the further research on the BiCMOS SRAM design.…”

Section: Introductionmentioning

confidence: 99%

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Design of BiCMOS SRAMs for high‐speed SiGe applications

LeRoy

Clarke

Chu

et al. 2014

IET Circuits, Devices & Systems

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This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.

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Section: Test and Measured Resultsmentioning

confidence: 98%

Section: Test and Measured Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of BiCMOS SRAMs for high‐speed SiGe applications

LeRoy

Clarke

Chu

et al. 2014

IET Circuits, Devices & Systems

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“…A number of solutions, such as BL twisting, have been proposed to reduce cross talk noise and increase the signal-noise ratio (SNR) [Ohhata92,Noda01]. These solutions, however, focus mainly on overcoming BL coupling from a design point of view, in order to prevent data destruction during a write operation [Takeda00], or in order to reduce the BL delay time during the precharge cycle, thereby increasing overall memory performance [Nambu95]. This section evaluates the impact of coupling on the faulty behavior of the SRAM.…”

Section: Effects Of Couplingmentioning

confidence: 99%

Evaluation of SRAM faulty behavior under bit line coupling

Al-Ars

Hamdioui

2008

2008 3rd International Design and Test Workshop

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The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty behavior of SRAM devices. Spice simulations are used to show how coupling can prevent the detection of otherwise detectable faults. Furthermore, an evaluation is done of the needed bit line coupling conditions to guarantee a high fault coverage of a given defect. This is done by identifying the most stressful data background patterns in the neighborhood of the faulty cell.

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“…Research on the impact of parasitic capacitance on the faulty behavior has up till now addressed faults in peripheral memory circuits as well as address decoders [14].A number of solutions, such as BL twisting, have been proposed to reduce cross talk noise and increase the signal-to-noise ratio [7], [8]. However, such solutions focus mainly on overcoming BL coupling from a design perspective and are expensive to implement making them infeasible in many applications [9], [6].…”

Section: Introductionmentioning

confidence: 99%

Bit line coupling memory tests for single-cell fails in SRAMs

Irobi

Al-Ars

Hamdioui

2010

2010 28th VLSI Test Symposium (VTS)

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Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper evaluates the impact of bit line coupling in SRAMs on cell faulty behavior and identifies necessary conditions to induce worst-case coupling effects.We present a test that guarantees detecting all singlecell static faults in the presence of capacitive coupling and worst-case neighborhood data for any possible open defect.

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A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Cited by 12 publications

References 31 publications

Design of BiCMOS SRAMs for high‐speed SiGe applications

Design of BiCMOS SRAMs for high‐speed SiGe applications

Evaluation of SRAM faulty behavior under bit line coupling

Bit line coupling memory tests for single-cell fails in SRAMs

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