A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

Farjad-Rad, R.; Yang, Chih-Kong Ken; Horowitz, Mark; Lee, T.H.

doi:10.1109/4.760366

Cited by 103 publications

(31 citation statements)

References 9 publications

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“…Since the transmitter operates from a fixed voltage supply, a maximum peak power limits the swing of the higher levels. One-tap amplitude pre-emphasis tends to provide some compensation for the frequency-dependent losses, however, more robust approaches use multiple taps to implement the transmit finite-impulse response (FIR) filter at the expense of additional power consumption [1], [2], [13].…”

Section: Amplitude Pre-emphasismentioning

confidence: 99%

“…Finding new methods to lower power consumption in serial links has been explored through low-common-mode signaling [10] and through low-supply operation [11]. Amplitude pre-emphasis distorts the signal to compensate ISI introduced by the bandwidth limitations of the interconnect [12], [13]. The number of taps of amplitude pre-emphasis depends on the channel quality and bit rate.…”

mentioning

confidence: 99%

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Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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Abstract-A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s.

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Section: Amplitude Pre-emphasismentioning

confidence: 99%

mentioning

confidence: 99%

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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“…Implementing a transmitter pre-shaping FIR filter requires only that the weighted adjacent bits need to be added to the transmitted signal to cancel the tail of the channel impulse response. The transmitter does not dictate the use of a faster technology to operate properly [7]. One way to implement an N-tap FIR filter is to make use of a digital to analogue converter (DAC) and a digital CMOS counter to adjust the FIR filter tap coefficients [7], as was implemented in this paper and is discussed in Section 4.…”

Section: Fir Pre-emphasis Filteringmentioning

confidence: 99%

“…A restriction of most widely implemented FIR filter pre-emphasis transmitters is that the coefficients of the FIR filter have been designed to be either fixed or externally adjustable [4,7,14,15]. Adaptive preemphasis is sought after to automatically adjust filter tap coefficients to provide an easy to use system with high data integrity.…”

Section: Fir Pre-emphasis Filteringmentioning

confidence: 99%

Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

Goosen

Sinha

2011

Microelectronics Journal

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Due to advances of technology in multimedia applications in recent years, the demand for high user end bandwidth point to point links has increased significantly. Jitter requirements have become ever more stringent with the increase in high speed serial link data rates. The introduced jitter severely degrades the performance of the high speed serial link. This paper introduces an adaptive FIR pre-emphasis technique as a means to alleviate the problem of limited off-chip bandwidth introducing data dependant jitter. Mathematical as well as SPICE simulation results are presented, together with the implemented integrated circuit layouts of the novel 0.18 μm CMOS implementation. Limited results from the experimentally tested IC are also presented and discussed. The adaptive pre-emphasis technique employed results in a simulated data dependant jitter reduction to less than 12.5 % of a unit interval at a data rate of 5 Gb/s and a modelled 30" FR-4 backplane copper channel.

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“…ISI is the major factor limiting the maximum distance and data rate of backplane data transmission. Using a symbol-spaced FIR filter for preemphasis at transmit side is a popular technique for counteracting ISI [1,2,3]. Traditionally, the symbol-spaced data for a multi-tap FIR filter is generated by employing a single-edge-triggered D flip-flop (DFF) with full-rate clock retiming.…”

Section: Introductionmentioning

confidence: 99%

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

Li¹,

Kwasniewski²,

Wang³

et al.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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Abstract-A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18µm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.

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A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

Cited by 103 publications

References 9 publications

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

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