A 0.18 μm CMOS implementation of on-chip analogue test signal generation from digital test patterns

Rolindez, L.; Mir, Salvador; Prenat, Guillaume; Bounceur, Ahcène

doi:10.1109/date.2004.1268939

Cited by 4 publications

(1 citation statement)

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“…Secondly, the out-of-band quantization noise present in the bit-stream can disturb the functionality of the CUT. In [11,13] an on-chip filter has been implemented to remove this quantization noise, but the quality of the analog signal was strongly reduced. In [14], the anti-aliasing filter present in the Σ∆ ADC was reused to filter the high-frequency noise, but this filter must be capable of accepting rail-to-rail input levels without causing distortions, which dramatically complicates its design and it is not feasible in high-resolution ADCs.…”

Section: International Test Conferencementioning

confidence: 99%

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

Rolindez

Mir

Carbonero

et al. 2007

2007 IEEE International Test Conference

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In this paper we present a new architecture for audio Analog-to-Digital Converters (ADCs) that includes a Built-In Self-Test (BIST) technique for the test of the Signal-to-Noise and Distortion Ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sinewave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 µm CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB. IntroductionIn order to satisfy the rising demand for high quality audio devices, the performances of Sigma-Delta Analog-toDigital Converters (Σ∆ ADCs) are continuously improving with larger modulator bandwidths and higher dynamic ranges. As the performances of these circuits increase, its test is in turn more difficult and costly. Built-In Self-Test (BIST) techniques can reduce this cost by integrating the test approach in the design phase.In the last years, an intense research effort has been carried out in order to find BIST solutions for ADCs. The Oscillation-based Built-In Self-Test (OBIST) was proposed in [1] for the calculation of the input transition voltages and non-linearity errors. The main advantage of this method is that we do not need to generate an analog input stimulus for the test. However, it does not measure dynamic parameters and it takes a long test time for high-resolution converters. The oscillation-based BIST has also been applied to the test of Σ∆ modulators [2], where the modulator is reconfigured to be an oscillator. Both the frequency and the amplitude of the oscillation are measured in order to separate faulty-circuits from faultfree ones. The need to modify the circuit and the sensibility to process variations can deteriorate the quality of this BIST approach.Other authors [3,4,5,6] have proposed the estimation of the leakage in the modulator integrators, which is directly related to the quantization noise present in the bandwidth of the modulator at its output. Additionally, the same approach is used in [6] for the estimation of the settlingtime. These approaches do not allow for a complete validation of the modulator and additional tests may be necessary. Furthermore, in [3] and [4] large digital resources are required.The histogram-based technique has also been applied to the BIST of ADCs in [7]. However, only static information is obtained and long test times are necessary when the number of ...

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Section: International Test Conferencementioning

confidence: 99%