A 0.11 μm CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores

Abstract

This paper describes a 0.11 p m CMOS technology with high-reliable copper and very-low-k (VLK) (kc2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 p m gate transistor, and 2.2 p mz 6T-SRAh4 cell are realized by using KrF 248nm lithography, opticalproximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63mA/ p m and 0.281nN p m are realized for nMOSFET and pMOSFET with 0.11 p m gate, respectively. Propagation delay of 2-input NAND with the copperlhybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 fi m CMOS technology with copper/FSG interconnects.

Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLK<SUP>T.M.</SUP>/SiO<SUB>2</SUB> Hybrid Structure

“…interconnection, where the interconnect length was 500 grids and a grid was equal to 0.4 µm, showed a 70% improvement compared to 0.18-µm CMOS technology with copper/FSG interconnection using this technology. 18,19) The simulated line capacitance in the M2 structure (k = 2.7, 4.1, and 7.0, respectively, for SiLK T.M. , SiO 2 , and SiN) was 160-170 fF/mm, which was close to the measured value.…”

<title>Impact of subwavelength CD tolerance on device performance</title>

“…Fig.2 shows a growing disparity between CD and λ, both shrinking in accordance with the SIA roadmap [1]. Designs for 100 nm technologies are currently reaching the limit of 248 nm lithography forcing the process to choose between switching to 193 nm steppers or extensively using resolution enhancement techniques (RET): phase shift (PSM) and other complex optical proximity correction (OPC) [2][3][4][5][6]. While the former solution suffers from substantial equipment cost, the latter bears a risk of limited lifetime [7].…”

“…Fig.4. Image qualification for MOSFET endcaps inside a 6T SRAM cell [2][3][4][5][6]: a) layout with OPC hammerhead on an FET endcap, b) proposed tolerance contours for two adjacent cell FETs, c) simulated intensity contours, difficult to qualify without tolerance contours, d) qualification becomes easy due to the introduction of tolerance contours, e) intensity contour simulation with defocus makes it almost impossible to judge layout quality, f) intensity contours simulated with defocus do not meet tolerance criteria, showing that OPC features need optimization, g) same tolerance criteria would necessitate different OPC corrections when poly proximity line is removed, h) the effect of defocus on poly proximity can be easily identified by referring to tolerance lines.…”

“…However, the progress has slowed down in the recent years due to the limitations of the lithography [2][3][4][5][6]. While individual FET gates are readily printed at 70-80 nm, proximity effects due to endcaps make it difficult to scale the cell area below 2 µm 2 [12,13].…”

Differential current-mode sensing for efficient on-chip global signaling

“…8) in 0.11 m, 1.2 V CMOS with copper interconnects, low-dielectrics, and dualFETs [8]. Eight metal layers are available in this CMOS process, with metal 1 to metal 4 targeted for local interconnects, and metal 5 to metal 8, which are thicker and have coarser pitch, targeted for semi-global and global interconnects.…”