Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLK<SUP>T.M.</SUP>/SiO<SUB>2</SUB> Hybrid Structure

Abstract

This paper describes a 0.13-µm CMOS made by using highly reliable copper and SiLK T.M. (DOW CHEMICAL) interconnection technologies. We propose a hybrid interlayer structure with SiLK T.M. at the trench level and SiO 2 at the via level to improve electrical properties, mechanical strength, and reliability. Using these technologies, we made a fully functional 1.5-Mbit SRAM macro and investigated the reliability of its copper wiring in terms of electromigration.

Characterization of Vacancy Defects in Electroplated Cu Films by Positron Annihilation and its Impact on Stress Migration Reliability

“…For SIV tests, a two level via chain structure was fabricated using 130-nm node technology [13][14]. A dual damascene process was used to fabricate M2 lines and vias.…”