Abstract:We present a new on-chip signaling method that relies on differential current-mode sensing to improve both delay and energy dissipation compared to conventional inverter repeaters. The proposed method can be used for point-to-point as well as -to-1 connections. Several experimental point-to-point transceivers with different interconnect length and an inverter repeater-based interconnect were implemented in 0.11 m, 1.2 V CMOS. Hardware measurements indicate that the proposed current-sensed transceiver produces … Show more
“…The resonance peak, therefore, shifts to a higher frequency. Note that the magnitude of the transfer function reaches 0.8 at a 5-GHz frequency, as determined from (5).…”
Section: Case Studymentioning
confidence: 65%
“…In this approach, a current sense amplifier at the far end of the line detects a current difference and converts it into a voltage difference. To improve both delay and energy dissipation, a transmitter generating a differential current detected by a current mode sense amplifier at the receiving end has been proposed in [5]. To accommodate differential operation, redundant circuitry is used.…”
Abstract-Design and analysis guidelines for quasi-resonant interconnect networks (QRN) are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain both low power and low latency. Excellent agreement is shown between the proposed model and SpectraS simulations. The analysis and design of the inductor, insertion point, and driver resistance for minimum power-delay product is described. A case study demonstrates the design of a quasi-resonant interconnect, transmitting a 5 Gb/s data signal along a 5 mm line in a TSMC 0.18-m CMOS technology. As compared to classical repeater insertion, an average reduction of 91.1% and 37.8% is obtained in power consumption and delay, respectively. As compared to optical links, a reduction of 97.1% and 35.6% is observed in power consumption and delay, respectively.
“…The resonance peak, therefore, shifts to a higher frequency. Note that the magnitude of the transfer function reaches 0.8 at a 5-GHz frequency, as determined from (5).…”
Section: Case Studymentioning
confidence: 65%
“…In this approach, a current sense amplifier at the far end of the line detects a current difference and converts it into a voltage difference. To improve both delay and energy dissipation, a transmitter generating a differential current detected by a current mode sense amplifier at the receiving end has been proposed in [5]. To accommodate differential operation, redundant circuitry is used.…”
Abstract-Design and analysis guidelines for quasi-resonant interconnect networks (QRN) are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain both low power and low latency. Excellent agreement is shown between the proposed model and SpectraS simulations. The analysis and design of the inductor, insertion point, and driver resistance for minimum power-delay product is described. A case study demonstrates the design of a quasi-resonant interconnect, transmitting a 5 Gb/s data signal along a 5 mm line in a TSMC 0.18-m CMOS technology. As compared to classical repeater insertion, an average reduction of 91.1% and 37.8% is obtained in power consumption and delay, respectively. As compared to optical links, a reduction of 97.1% and 35.6% is observed in power consumption and delay, respectively.
“…It can operate at a much lower noise margin than the voltage-mode network, and at a much lower swing as well due to its immunity to power supply noise. All these translate into increased bandwidth performance [16], decreased delay and dynamic power dissipation and higher noise immunity. For these reasons, CMS technique becomes a better alternative than VMS scheme for on temporary and future high-speed noise-prone single chip systems.…”
Section: A Using Shield Insertion For Delay Reductionmentioning
Abstract-With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.
“…However, in many implementations [65][66][67][68][69][70][71][72], current-sensing amplifiers with low input impedance are used to create the resistive receiver impedance. A current-sensing receiver based on a trans-impedance amplifier, as shown in Figure 4.6a, was also used in this project [33,73].…”
Section: Circuit-level Differences Between Resistive and Capacitive Tmentioning
confidence: 99%
“…Sense amplifiers (SA) are hence widely applied in e.g. logic, memories, I/O data receivers [158], A/D converters [159][160][161][162], and more recently also in on-chip transceivers [20,33,61,67,69,72,77,84,85,121,124].…”
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