A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

Yu, Haohong; Chen, Yong; Boon, Chirn Chye; Mak, Pui-In; Martins, Rui P.

doi:10.1109/tmtt.2019.2949796

Cited by 76 publications

(21 citation statements)

References 34 publications

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“…It can be seen that the implemented BLE receiver is the most power-efficient compared to the previous state-of-the-art RF-to-BB-CR receivers of [8]- [11] while satisfying all the requirements of the BLE standard. Research on the quadrature RF-to-BB-CR receiver architecture using noise-cancelling techniques [31]- [34] could be a future study to realize low-power and low-noise BLE receivers for IoT applications.…”

Section: Resultsmentioning

confidence: 99%

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

Park

Kwon

2021

IEEE Access

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In this paper, a 2.4 GHz Bluetooth low energy receiver employing a power-efficient quadrature RF-to-baseband-current-reuse architecture is presented for low-power low-voltage internet of things applications. The proposed quadrature RF-to-baseband-current-reuse RF front-end consists of a lownoise transconductance amplifier, an active-type polyphase filter-based quadrature generator, transimpedance amplifiers, and double-balanced current-mode passive mixers on a single dc current path. An input matching network is used to perform power-constrained simultaneous noise and input power matching and 1/f noise reduction in the RF and baseband domains, respectively. The quadrature RF signals are provided to the single-quadrature mixers through an embedded active-type polyphase filter-based quadrature generator. The implemented Bluetooth low energy receiver is composed of the RF-to-basebandcurrent-reuse RF front-end, IF amplifiers, two-stage passive-RC polyphase filter, and fifth-order Chebyshev-II G m -C filters. The proposed design was fabricated using a 65-nm CMOS process and characterized primarily in the Bluetooth low energy operating frequency bands. The active die area of the implemented receiver was 0.85 mm 2 , and the receiver drew a bias current of 1.41 mA from a nominal supply voltage of 0.8 V. The Bluetooth low energy receiver achieved a noise figure of 13.2 dB, conversion gain of 42 dB, image rejection ratio of more than 30 dB, and input-referred third-order intercept point of −25 dBm.INDEX TERMS Active-type polyphase filter, bias-current sharing, Bluetooth low energy, current-reuse, image rejection ratio, IoT, I/Q mismatch, low-IF receiver, low-voltage, non-invasive filter, quadrature generator, quadrature transconductor, RF-to-BB-current-reuse

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Section: Resultsmentioning

confidence: 99%

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

Park

Kwon

2021

IEEE Access

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“…However, these receivers provide such performance parameters over a relatively narrow bandwidth of 2.7 GHz. Similarly, the works in [24,25] provide competitive LNA architectures over extremely wide RF bandwidths. However, based on the post-layout simulation results, the proposed LNA provides even better performance in terms of gain, NF, and input matching as compared to these works.…”

Section: Measurement Resultsmentioning

confidence: 99%

A Ku-Band RF Front-End Employing Broadband Impedance Matching with 3.5 dB NF and 21 dB Conversion Gain in 45-nm CMOS Technology

et al. 2020

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This paper presents a K u -band RF receiver front-end with broadband impedance matching and amplification. The major building blocks of the proposed receiver front-end include a wideband low-noise amplifier (LNA) employing a cascade of resistive feedback inverter (RFI) and transformer-loaded common source amplifier, a down-conversion mixer with push–pull transconductor and complementary LO switching stage, and an output buffer. Push–pull architecture is employed extensively to maximize the power efficiency, bandwidth, and linearity. The proposed two-stage LNA employs the stagger-tuned frequency response in order to extend the RF bandwidth coverage. The input impedance of RFI is carefully analyzed, and a wideband input matching circuit incorporating only a single inductor is presented along with useful equivalent impedance matching models and detailed design analysis. The prototype chip was fabricated in 45-nm CMOS technology and dissipates 78 mW from a 1.2-V supply while occupying chip area of 0.29 mm 2 . The proposed receiver front-end provides 21 dB conversion gain with 7 GHz IF bandwidth, 3.5 dB NF, −15.7 dBm IIP 3 while satisfying <−10 dB input matching over the whole input band.

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“…By combining the noise-canceling principles in Fig. 1(a) and (b), narrow [24] and wideband [25] dual-path noise-canceling LNAs with reduced noise of both main and auxiliary paths are reported with enhanced NF performance. Nonetheless, due to the relatively large effects This work is licensed under a Creative Commons Attribution 4.0 License.…”

Section: Introductionmentioning

confidence: 99%

A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS

Deng

Zhou

Qian

et al. 2021

IEEE J. Solid-State Circuits

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In this article, a 22.9-38.2-GHz dual-path noisecanceling low noise amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by reducing the noise of both paths. Such LNA consists of one common gate (CG) amplifier with one three-stage transformer, one resistive feedback common-source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-stage transformer is used in the CG amplifier to provide gain-boosting, noise-reducing, and wideband inter-stage matching operation, simultaneously. Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning lines are utilized in both paths to optimize the noise-canceling performance. To verify the aforementioned principle, a dualpath noise-canceling LNA is implemented and fabricated using a conventional 28-nm CMOS technology. The proposed LNA consumed 18.9 mW under a 0.9-V supply. The measured NF is 2.65-4.62 dB within the operating frequency range of 22.9-38.2 GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression point (IP 1 dB ) and input third-order intercept point (IIP3) are −13.2 to −6.6 and −3.6 to 3.2 dBm, respectively.

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A 0.096-mm$^{2}~1$ –20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration

Cited by 76 publications

References 34 publications

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

A Ku-Band RF Front-End Employing Broadband Impedance Matching with 3.5 dB NF and 21 dB Conversion Gain in 45-nm CMOS Technology

A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS

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