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Chang, Soon-Jyh; Lee, Chung Len; Chen, Jwu E.

doi:10.1023/a:1020892721493

Cited by 8 publications

(1 citation statement)

References 18 publications

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“…In order to eliminate the voltage discontinuity at MOS gate terminals, the transistor gate opens were distinctively modeled by connecting a large 10-MΩ resistor to gate and disconnecting terminals with respect to the system ground. In the case of parametric faults, the component variation was realized where the practical component variations are in an extensive range from 10% to 50% [19][20]. In summary, the total number of 54 faults was investigated, including 13 faults in the linear RC network and 41 faults in the unity-gain buffer.…”

Section: Preliminary Evaluations Of Fault Influencesmentioning

confidence: 99%

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

San-Um

Tachibana

2009

ECTI-EEC

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This paper presents a pulse response-based builtin self test technique and implementation for the testing of analog integrated circuits in mixed-signal systems. This BIST technique employs two narrow width pulses as input stimuli, and monitors two voltage samples on pulse response waveform for fault detection through allowable tolerances. The BIST system implementation realizes a programmable delay line for generating pulse stimuli, and a sample-and-hold circuit with comparators for fault detection process. Demonstrations of the testing for a Sallen-Keylow-pass ¯lter using 0.18-?m CMOS technology yields relatively high fault coverage. The fault coverage of catastrophic faults is 100%, and the fault coverage of capacitor and resistor variations are 93.75% and 87.5%, respectively. The proposed BIST technique uses low testing time within two short pulse response waveforms, and o®ers low implementation cost since onchip sinusoidal stimuli, test algorithms, and external digital processing unit are not necessary.

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Section: Preliminary Evaluations Of Fault Influencesmentioning

confidence: 99%

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

San-Um

Tachibana

2009

ECTI-EEC

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Digital-Compatible Testing Scheme for Operational Amplifier

Ting

2012

J Electron Test

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This paper presents a digital-compatible testing scheme for operational amplifier (op amp). In the proposed scheme, the op amp device under test (DUT) is configured to a unity-gain buffer which is responded to a testing pulse, could be realized by a ring oscillator circuit. The output of the configured unity-gain buffer is digitized by simple digital counter and then the digitized counting number is compared to a predetermined critical value to evaluate the op amp DUT. The digitized counting number is sensitive to the specification of op amp DUT and easily to be observed in the digital domain. The testing parameters of testing setup of stimulus, testing result, testing accuracy, and testing time are also investigated to detail the proposed scheme. Digital compatibility and simplicity are main advantages of the proposed testing scheme. In addition, no complicated analog comparator and reference voltages are required. Behavioral and circuit level simulations are performed to show the effectiveness of the proposed scheme.

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An Infrastructure for Analog Circuits Testing

Ting

Yang

2012

2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop

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Untitled

Cited by 8 publications

References 18 publications

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits

Digital-Compatible Testing Scheme for Operational Amplifier

An Infrastructure for Analog Circuits Testing

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