An Infrastructure for Analog Circuits Testing

Ting, Hsin-Wen; Yang, Cing-Wen

doi:10.1109/ims3tw.2012.31

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2015

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“…However, a generic solution should result from a cooptimization combining observability and controllability in a flexible way. This has been presented in [10] [11]. In the same way as for digital testing, scan-chains have been added to observe node voltage and inject signals at specific nodes.…”

Section: Introductionmentioning

confidence: 99%

Automated testing of mixed-signal integrated circuits by topology modification

Coyette

Esen

Vanhooren

et al. 2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.

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Section: Introductionmentioning

confidence: 99%