A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.

Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimizationVLSI, the integration, vol 55, p. 393-400.

The detection level of defects in today's mixedsignal ICs lags behind the extremely high demand of industries such as automotive. This is mainly because analog blocks in these ICs have high test escape rates as a result of the typical testing based on the performance specifications. Defect-oriented techniques have been proposed to solve the problem of this poor fault coverage for analog circuits. Their effectiveness in practice is however still limited due to the inadequate fault models used to represent physical failures. This paper presents a new open-gate DC fault model. Experimental results on fabricated test circuits in 0.35µm BCD technology are used to validate the proposed fault model and the commonly used high-value-resistance model. Finally, a new testing approach to detect the corresponding open defects in analog circuits is discussed, which is based on forcing the transistors outside their designed operation region.

Electronics are increasingly being embedded in a growing number of applications in our daily life. This demands strong reliability and robustness of those electronic systems. The IC manufacturing process not being perfect, however, inevitably results in some fabricated parts having defects. Test methods must detect such faulty ICs before shipment. While the fault coverage of testing for digital integrated circuits in industry today already reaches the sub-ppm level, this is not yet the case for analog integrated circuits or the analog part in mixed-signal ICs. This invited talk will review some techniques that are being explored in industrial practice to aim for sub-ppm-level coverage for the analog and mixed-signal circuits as well. This will be illustrated with some practical examples from automotive IC designs.

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