2014 International Test Conference 2014
DOI: 10.1109/test.2014.7035330
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Design and test of analog circuits towards sub-ppm level

Abstract: Electronics are increasingly being embedded in a growing number of applications in our daily life. This demands strong reliability and robustness of those electronic systems. The IC manufacturing process not being perfect, however, inevitably results in some fabricated parts having defects. Test methods must detect such faulty ICs before shipment. While the fault coverage of testing for digital integrated circuits in industry today already reaches the sub-ppm level, this is not yet the case for analog integrat… Show more

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Cited by 19 publications
(7 citation statements)
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“…Thus, each sub-DAC can set 2 5 − 1 = 31 comparison levels. VREF [1] to VREF [31] denote these comparison levels, VREF[0]=GND, and VREF [32]=VREFP. The midscale voltage is VREF [16].…”
Section: A Sar Adc Principlementioning
confidence: 99%
See 2 more Smart Citations
“…Thus, each sub-DAC can set 2 5 − 1 = 31 comparison levels. VREF [1] to VREF [31] denote these comparison levels, VREF[0]=GND, and VREF [32]=VREFP. The midscale voltage is VREF [16].…”
Section: A Sar Adc Principlementioning
confidence: 99%
“…This implies that the functional safety of individual ICs must increase to prevent decrease in the system's functional safety. More specifically, it is desired that test escapes are in the order of sub-ppm [1].…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…This empirical approach results in long and expensive test sets which cause analog testing to dominate the testing effort and cost for mixed-signal ICs. Furthermore, these specification-based tests often lead to poor fault coverage for the analog circuits, since the possible defects are not directly addressed in such a methodology [1].…”
Section: Introductionmentioning
confidence: 99%
“…This rather empirical approach results in long and expensive test sets which cause analog testing to dominate the testing effort and cost for mixed-signal ICs. Furthermore, these specification-based tests often lead to poor fault coverage, since the possible defects are not directly addressed in such a methodology [2], [3].…”
Section: Introductionmentioning
confidence: 99%