70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I on /I off ).Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices.

Section: Underlap Design For Itrs Projectionsmentioning

confidence: 99%

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

Kranti¹,

Hao²,

Armstrong³

2008

“…∼4 orders of magnitude reduction at the gate edge relative to peak S/D doping value. Since the value of d depends on thermal budget and diffusivity, very small values (<3 nm dec −1 ) may be difficult to achieve (very small values of d require a nonstandard process [49,50] such as solid phase epitaxy or laser thermal annealing) as it may ultimately require control of individual atoms. Therefore, it is more appropriate to increase s to achieve higher s/σ values.…”

Section: Underlap Ota Designmentioning

confidence: 99%

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

Kranti¹,

Rashmi²,

Armstrong³

2009

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A VO OTA ) > 55 dB and unity gain frequency (f T OTA ) ∼ 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A VO OTA and three fold enhancement in f T OTA over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A VO OTA values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f T OTA values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A VO OTA and f T OTA highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/σ ) ratio of 3.2 and operated below a bias current (I BIAS ) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

“…Thus, improving SCEs in devices with high-κ gate dielectrics requires an increase in L eff by increasing ρ, i.e., reducing d for the same value of s or increasing s for the same d. In an optimal design, it is more appropriate to change spacer values as the minimum value of d is generally set by the thermal budget and the diffusivity of the dopant species. Very small values of d (∼2 nm/decade) are indeed very aggressive and therefore may require a non-standard process [33,34] such as solid phase epitaxy or laser thermal annealing in order to be practically feasible.…”

Section: Source/drain Extension Region Optimizationmentioning

confidence: 99%

Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics

Kranti

Armstrong

2006

In the present paper, we propose a new scaling theory to model short channel effects (SCEs) in nanoscale double gate (DG) SOI MOSFETs, addressing two important technological issues-source/drain extension (SDE) region engineering and high-κ gate dielectrics. The impact of SDE region engineering through the optimization of lateral source/drain doping gradient and spacer width on SCEs is extensively analysed in DG devices with high-κ gate dielectrics, using the analytical model and 2D device simulations. Novel technology dependent scaling parameters, i.e., spacer-to-gradient ratio (ρ) and effective channel length (L eff ), are proposed for source/ drain-engineered DG MOSFETs, and their significance in minimizing SCEs in high-κ gate dielectrics is discussed in detail. Results show that the optimal spacer-to-gradient ratio should be increased with the permittivity of high-κ dielectrics in order to maintain SCEs to an acceptable level. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients, high-κ gate dielectrics and effective channel lengths. The present work provides valuable design insights in the performance of nanoscale source/drain-engineered DG SOI devices with high-κ gate dielectrics and serves as an accurate tool to optimize important device parameters aiding technology development.