Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics

Abstract

In the present paper, we propose a new scaling theory to model short channel effects (SCEs) in nanoscale double gate (DG) SOI MOSFETs, addressing two important technological issues-source/drain extension (SDE) region engineering and high-κ gate dielectrics. The impact of SDE region engineering through the optimization of lateral source/drain doping gradient and spacer width on SCEs is extensively analysed in DG devices with high-κ gate dielectrics, using the analytical model and 2D device simulations. Novel technology dependent scaling parameters, i.e., spacer-to-gradient ratio (ρ) and effective channel length (L eff ), are proposed for source/ drain-engineered DG MOSFETs, and their significance in minimizing SCEs in high-κ gate dielectrics is discussed in detail. Results show that the optimal spacer-to-gradient ratio should be increased with the permittivity of high-κ dielectrics in order to maintain SCEs to an acceptable level. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients, high-κ gate dielectrics and effective channel lengths. The present work provides valuable design insights in the performance of nanoscale source/drain-engineered DG SOI devices with high-κ gate dielectrics and serves as an accurate tool to optimize important device parameters aiding technology development.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

“…Even though the back gate cannot effectively control the channel potential due to the misalignment, subthreshold slope (S-slope) values are better/comparable than exhibited by self-aligned DG devices (with abrupt S/D regions) for r P 10 nm. Underlap design results in a longer effective channel length (L eff ) [15,16,22] due to the additional contribution from the S/D extension regions thus suppressing SCEs. The S-slope values for the devices analyzed in Table 1 suggest that r P 10 nm is advantageous to maximize g m /I ds in subthreshold region (S-slope = ln(10)/(g m /I ds ) peak ).…”

“…Source/Drain (S/D) profile (Fig. 1b) was modeled using the expression N SD (x) = (N SD ) peak exp(-x 2 /r 2 ), where (N SD ) peak is the peak S/D doping, r (lateral straggle) defines the roll-off [13][14][15][16][17][18] of the Gaussian S/D profile as ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2sd=lnð10Þ p , s is the spacer width. The S/D doping gradient (d) which provides a measure of lateral doping abruptness was evaluated as (d = 1/|dN SD (x)/dx|) [13][14][15][16][17][18][19] at the front gate edge and was varied from 3 to 5 nm/decade.…”

“…In this work, we propose a design methodology to alleviate the above two critical issues for ultra-low-voltage (ULV) analog/rf devices operating in the subthreshold and low moderate inversion regions. We use the concept of gate-underlap design which has been studied extensively for digital [12][13][14][15][16][17][18] and analog/rf [19][20][21][22][23] applications. In high-volume manufacturing, gate-source/drain underlap devices were 'accidentally' fabricated in 0.35 micron CMOS technology [24].…”

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

“…In the underlap region, the depletion layer boundary (i.e., the position in the channel where the electron concentration is lower than the net doping) at the source (or drain) edge depends on s and d. Therefore, as shown in Fig. 3(a), the contribution of the SDE region to L eff can be taken as the distance from the depletion layer boundary (at source/drain end) to the gate edge [18]. Fig.…”

Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with architecture “without overlapping”

“…For a definition of a region of acceptable values (RAVs) of topological parameters, it is necessary to satisfy a number of criteria, which follow from the technology requirements [3,[5][6][7]: (1) L eff /l > 2, where l is the characteristic length; (2) L eff > L g , where is the gate length; (3) 6 nm ≤ σ ≤ 8 nm, where σ = is the parameter determining the slope of an impurity profile in the longitudinal direction (along the chan nel), where the scaling parameter η is entered as η = L s /L g ; (4) g ≥ 3 nm/dec. ; (5) t Si ≥ 6 nm, where t Si is the thickness of the working area; and (6) t f > 1 nm, where t f is the thickness of the frontal gate oxide.…”