6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2V<sub>ppd</sub> Output Swing in 7nm FinFET

Groen, Eric; Boecker, Charlie; Hossain, Masum; Vu, Roxanne; Vamvakos, Socrates D.; Lin, Haidang; Li, Simon; Ierssel, Marcus van; Choudhary, Prashant; Wang, Nanyan; Shibata, Masumi; Taghavi, Mohammad Hossein; Nguyễn, Nam Thành; Desai, Shaishav

doi:10.1109/isscc19947.2020.9063130

Cited by 31 publications

(12 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The following must be considered when comparing the equalized signal swings: de-embedding is used in [7], the extent to which is not specified. Packaged DACs [5], [6] incurred loss from the package and PCB trace which [5] partially compensated using oscilloscope equalization whereas [6] employed package loss de-embedding. Due to their higher symbol rate, [4], [6] are more affected by equipment bandwidth limitations.…”

Section: Resultsmentioning

confidence: 99%

A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

Moeneclaey

Verplaetse

Ramon

et al. 2021

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

View full text Add to dashboard Cite

We present a 6-bit 56-GSa/s digital-to-analog converter (DAC), implemented in 55 nm SiGe BiCMOS. It consumes 2.36 W of which 0.77 W is utilized in the DAC core. Experiments show an analog 3-dB bandwidth exceeding 28 GHz and an effective number of bits (ENOB) of 3.9. We demonstrate transmission of 112 Gb/s four-level pulse-amplitude modulation (PAM-4) and 168 Gb/s PAM-8 over a channel consisting of an electrical probe and 20 cm RF cables. With pre-equalization compensating the channel loss, we achieve a 0.59 Vpp signal swing.

show abstract

Section: Resultsmentioning

confidence: 99%

A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

Moeneclaey

Verplaetse

Ramon

et al. 2021

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

View full text Add to dashboard Cite

show abstract

“…Wireline transceivers have steadily pushed for greater speeds, reaching rates as high as 112 Gb/s through the use of PAM4 signaling [12]- [14]. It is expected that the next generation will rise to 224 Gb/s [15].…”

Section: The Need For Low Jittermentioning

confidence: 99%

Jitter-Power Trade-Offs in PLLs

Razavi

2021

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.

show abstract

“…The four-level amplitude modulation technique (PAM-4) can mitigate the bandwidth requirements [1]- [3]. the digital domain equalization technique improves the attenuation compensation ability by using the AD/DA converter to perform complex calculations in the digital domain [4]- [7].…”

Section: Introductionmentioning

confidence: 99%

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Ding

Jin

Zhou

2022

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

This brief presents A 16/32 Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067 mm 2 , while the proposed linearity enhanced part is 0.05×0.02 mm 2 and the total power consumption is 64.6 mW with a 1.1 V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.

show abstract

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2V_ppd Output Swing in 7nm FinFET

Cited by 31 publications

References 3 publications

A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

Jitter-Power Trade-Offs in PLLs

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Contact Info

Product

Resources

About

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET

Cited by 31 publications

References 3 publications

A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS

Jitter-Power Trade-Offs in PLLs

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Contact Info

Product

Resources

About

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2V_ppd Output Swing in 7nm FinFET