50-GHz Interconnect Design in Standard Silicon Technology

Kleveland, B.; Lee, Thomas H.; Wong, S.S.

doi:10.1109/arftg.1998.327295

Cited by 40 publications

(33 citation statements)

References 10 publications

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“…With appropriate sizing, and through exploitation of many metal layers (or, more significantly, thicker total insulation between line and substrate), signal attenuations as low as 0.3 dB/mm at 50 GHz have been demonstrated with conductor dimensions and spacings corresponding to CMOS technologies to be deployed in the near future [25]. This value is comparable to the best of those achieved in any IC technology, and, therefore, should not pose a serious limit.…”

Section: Circuits Beyond 5 Ghzsupporting

confidence: 55%

“…Furthermore, other passive components, such as inductors, capacitors, and resonators, can be constructed out of transmission lines. The line attenuation factors imply that values of these other components will not suffer a precipitous drop with frequency, so it appears that passive components with acceptable quality will continue to be available well beyond 5 GHz [25].…”

Section: Circuits Beyond 5 Ghzmentioning

confidence: 99%

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CMOS RF integrated circuits at 5 GHz and beyond

Lee¹,

Wong²

2000

Proc. IEEE

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Section: Circuits Beyond 5 Ghzsupporting

confidence: 55%

Section: Circuits Beyond 5 Ghzmentioning

confidence: 99%

CMOS RF integrated circuits at 5 GHz and beyond

Lee¹,

Wong²

2000

Proc. IEEE

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“…A testchip was implemented in a triple metal (AlCu) 0.5-m CMOS technology. Line widths in the range 10 to 20 m are typical for low-loss transmission lines on Si substrate [2], [7]. To emulate the top level metal of an advanced process with thick and low resistivity material such as Cu, wider lines were used.…”

Section: Methodsmentioning

confidence: 99%

“…The distributed device would seem to exaggerate this nonuniformity. However, if low-resistive lines that are common in highfrequency designs are used [2]- [4], [7], the voltage drop due to metal line ohmic heating during the ESD event could be minimal [8], [9]. A small resistor in series with the ESD devices could further improve the snap-back triggering uniformity [10].…”

Section: Distributed Esd Designmentioning

confidence: 99%

Distributed ESD protection for high-speed integrated circuits

Kleveland¹,

Maloney

Morgan

et al. 2000

IEEE Electron Device Lett.

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Abstract-Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance-matched transition from the package to the chip. A simple resistive model adequately predicts the ESD behavior under stress according to the charged device and human body models. The large area of the distributed ESD scheme would limit its application to designs such as distributed amplifiers, rf transceivers, A/D converters, and serial links with only a few dedicated high-speed interfaces. The distributed ESD protection is compatible with high-speed layout guidelines, requiring only low-loss transmission lines in addition to a conventional ESD device.

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“…Thicker metals reduce conductor loss, and larger metal-to-substrate distance decreases parasitic capacitance and dielectric loss. These changes in metals have significantly improved the performance of on-chip transmission lines in silicon, which not only benefits highspeed interconnects [2], but also enables constructing passive devices for microwave and millimeter-wave applications [3].…”

Section: Introductionmentioning

confidence: 99%