5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology

Yeung, Alfred; Partovi, H.; Harvard, Qawi; Ravezzi, L.; Ngai, John; Homer, Russ; Ashcraft, Matthew B.; Favor, Greg

doi:10.1109/isscc.2014.6757360

Cited by 14 publications

(5 citation statements)

References 3 publications

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“…And then 64-bit processor becomes the main stream in architecture field to achieve high-performance computing in these days. Currently, even mobile processors such as ARM [19] has 64bit capable. Therefore, as a branch project of FabScalar, there is FabScalar-alpha which adopts Alpha 21264 ISA.…”

Section: Fabscalar-alphamentioning

confidence: 99%

Evaluation of Portability and Design Diversity of FabCache

Sasaki¹,

Okamoto²,

Miyoshi³

et al. 2016

IJCEE

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Single-ISA heterogeneous multi-core architecture which consists of diverse superscalar cores is becoming more importantly in the processor architecture. Using a proper superscalar core for characteristic in a program contributes to reduce energy consumption and improve performance. However, designing a heterogeneous multi-core processor requires a large design and verification effort. Therefore, we have proposed FabHetero which generates diverse heterogeneous multi-core processors automatically using FabScalar, FabCache, and FabBus which generate various designs of superscalar core, cache system, and flexible shared bus system, respectively. In our previous work, we estimated the physical design, delay, and power consumption only on a L1 instruction cache of a 32-bit processor. However, almost all modern processor has a L1 data cache, and nowadays there are many 64-bit processors to achieve high-performance computing. This paper shows availability and efficiency of the FabCache by estimating overheads, area, delay, and power consumption, of both instruction cache and data cache systems for both 32-bit and 64-bit processors. FabCache has good portability because bus communication system of generated cache system from FabCache employs AMBA4 protocol that is widely used in various architecture to communicate with other design and its connection logic can be parameterized such as individual bus width. To show an effectiveness and portability of FabCache, this paper applies FabCache to FabScalar-alpha which is a 64-bit processor, and evaluates availability and effectiveness of the generated cache system. According to the evaluation results, the cache systems generated by FabCache works perfectly and the increased area is about 1.7%, delay is 0.1ns, and power is 0.1% compared with hand designed cache system. Evaluation results show that the FabCache can generate reasonable cache system and it has good portability.

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Section: Fabscalar-alphamentioning

confidence: 99%

Evaluation of Portability and Design Diversity of FabCache

Sasaki¹,

Okamoto²,

Miyoshi³

et al. 2016

IJCEE

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“…The subsequent sections of this paper describe circuit-level techniques and innovations in the design construction flow that allowed the team to overcome the challenges and deliver a product with industry-leading performance. The reader is directed to [9][10][11][12] for related papers in the area of processor design for high performance at limited power budget.…”

Section: Chip Overviewmentioning

confidence: 99%

IBM POWER8 circuit design and energy optimization

Zyuban

Friedrich

Dreps³

et al. 2015

IBM J. Res. & Dev.

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The IBM POWER8i processor is a 649-mm 2 , 4.2-billion transistor, high-frequency microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth shared third-level cache, and increased on and off-chip bandwidth, the POWER8 processor delivers industry-leading performance. This paper describes the circuit techniques and design methodologies that were employed for implementing this chip and that allowed it to maintain the power dissipation at the level of its predecessor while delivering a threefold increase in per-socket performance. Among the innovative technologies employed by the processor are resonant clocking, on-chip per-core voltage regulation, and enhanced eDRAM arrays. Chip overviewThe IBM POWER8* processor [1,2] is the eighth generation of IBM Power Architecture* implemented in IBM's 22-nm embedded dynamic random access memory (eDRAM) silicon on insulator (SOI) technology [3]. The 649 mm 2 POWER8 processor die includes twelve architecturally enhanced eight-way multithreaded cores with high-throughput private second-level caches, a 96-MB high-bandwidth eDRAM third-level cache, an on-chip symmetric multi-processor (SMP) fabric, a set of cryptography and memory compression accelerators, memory controllers with I/O links capable of connecting to a maximum of eight memory buffer chips [4], six high-bandwidth off-chip SMP links, and 32 third-generation PCI Express** (PCIe**) lanes. Figure 1 shows the die photograph of the POWER8 processor. The processor cores are grouped into four quadrants. Each core has a private 512-KB level-2 (L2) cache with a read bandwidth of 64 bytes per cycle. The shared 96-MB level-3 (L3) cache is physically placed into the core quadrants. The on-chip SMP buses connecting the processor cores, memory controllers, accelerators, and I/O units are running through the horizontal stripe in the center of the chip, referred to as Fabric in Figure 1, and the vertical wiring channel in the middle. The on-node SMP buses, responsible for intra-node communication, are located along the top edge of the die, while the off-node SMP buses, responsible for inter-node communication, are located along the bottom edge together with the PCIe links. The memory links connecting the POWER8 processor to a maximum of eight memory buffer chips are located on the left and right side of the die. The accelerator units are located between the two core quadrants in the upper half of the processor die. The POWER8 processor contains approximately 4.2 billion transistors. Compared to its predecessor, the POWER7* processor [2, 5, 6], the POWER8 chip achieves a 50% improvement in single-thread performance, a two-fold increase in the per-core performance, and a three-fold increase in the chip throughput when measured at the same frequency [7]. In terms of the maximum core and SMP bus frequencies, the POWER8 processor achieves an incremental ...

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“…The impact of temperature variations was evaluated through the sensitivity to temperature around the nominal operating value of 85°C, as typical of microprocessor systems [101,143,150].…”

Section: Impact Of Temperature Variationsmentioning

confidence: 99%