4 × 4 2-D DCT for H.264/AVC

Prasoon, Adhish; Rajan, K.

doi:10.1145/1523103.1523218

Cited by 9 publications

(6 citation statements)

References 10 publications

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“…Practical DCT implementations can adopt a sequential three-step approach [2], where the first step implements an one-dimensional matrix transform (horizontal direction), the second step performs a matrix transposition operation (horizontal to vertical) and the thirty step implements finally the matrix transform in vertical direction. The inverse DCT algorithm is strongly similar to the direct algorithm only changing the matrix A (Figure 1b), e.g.…”

Section: A Discrete Cosine Transformmentioning

confidence: 99%

“…In this solution, "DCT_in" represents the input array while "num_in" indicates its corresponding position inside the source macroblock (16x16 block). It is important to observe that arithmetic operations (add and shift) increase the output bit range in three bits [2], resulting in an output of 14-bits per sample. The 56-bits path of "DCT_out" represents the four samples output vector (4 x 14 bits = 56 bits).…”

Section: B Discrete Cosine Transformmentioning

confidence: 99%

“…However, when data dependency is strongly present (case of the most video encoding modules) the global core performance will depend directly on the slowest internal module, which generally can represent the most critical bottleneck [2].…”

Section: Introductionmentioning

confidence: 99%

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Hardware integrated quantization solution for improvement of computational H.264 encoder module

Hüsemann

Majolo

Guimarães

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamardand Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

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Section: A Discrete Cosine Transformmentioning

confidence: 99%

Section: B Discrete Cosine Transformmentioning

confidence: 99%

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Hardware integrated quantization solution for improvement of computational H.264 encoder module

Hüsemann

Majolo

Guimarães

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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“…Observing that the transform matrices A and A T are defined as [7]: Note that, to implement operations with these matrices there are only needed simple hardware operators like adders, subtractors and shifters (one bit shifted in left direction performs a multiplication by two) [14].…”

Section: Amentioning

confidence: 99%

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder

Hüsemann

Majolo

Susin

et al. 2010

2010 IEEE Computer Society Annual Symposium on VLSI

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The computational-intensive demands of H.264 video encoder normally imply to the use of high performance hardware solutions like dedicated multimedia DSP or programmable logic devices. These demands can be even more critical when it is necessary to implement a H.264/SVC (Scalable Video Coding) solution, an emergent encoder standard that provides the generation of flexible and adaptive multi-layer streams. The complexity of a SVC encoder increases proportionally with number of configured layers, introducing new challenges to multimedia market. In this work we propose an efficient hardware module, responsible for the transform algorithms (Hadamard and DCT) of a SVC encoder, processing up eight samples per clock. The proposed module take into account specific memory demands in order to produce an optimized solution with respect to encoder performance and complexity, aiming to reach a realizable SVC encoder.

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“…Later advances in the research of DCT algorithms include radix-2 n DCT [5], mixed-radix DCT [6] and prime-factor DCT [7]. The most recently published algorithms such as matrix factorization [8], radix-q & mixed-radix DCT [9], reconfigurable DCT [10] and area optimal DCT [11] belong to the direct category.…”

Section: Introductionmentioning

confidence: 99%

Memory access reduction method for efficient implementation of vector-radix 2D fast cosine transform pruning on DSP

Wang

2010

Proceedings of the IEEE SoutheastCon 2010 (SoutheastCon)

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In this paper, we propose a novel memory access reduction method to minimize the memory accesses due to weighting factors (cosine coefficients in the computation diagram of vector-radix 2D FCT pruning) and input points for implementing vector-radix 2D FCT pruning on DSP processors. The proposed method reduces the number of memory accesses in two steps: 1) Reduce the number of weighting factors and 2) Combine butterflies at two stages in vector-radix 2D FCT pruning diagram to form an efficient butterfly structure in one stage and calculate them. The proposed method is applied to implement vector-radix 2D FCT pruning on TI TMSC320C64x DSP. Experimental results show that the proposed method can achieve average of 47.2% memory access reduction, average of 58.2% clock cycle reduction and average of 20% memory space saving for weighting factors to compute vectorradix 2D fast cosine transform pruning on DSP comparing with the conventional implementation.

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4 × 4 2-D DCT for H.264/AVC

Cited by 9 publications

References 10 publications

Hardware integrated quantization solution for improvement of computational H.264 encoder module

Hardware integrated quantization solution for improvement of computational H.264 encoder module

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder

Memory access reduction method for efficient implementation of vector-radix 2D fast cosine transform pruning on DSP

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