3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

Bae, Gyu-Jin; Bae, Dong-il; Kang, Mingu; Hwang, Soonkyu; Kim, S.S.; Seo, Bong-Gun; Kwon, Taegyun; Lee, T.J.; Moon, Cheol; Choi, YoungRok; Oikawa, Keiko; Masuoka, S.; Chun, Ki-Chul; Shin, Hong-Jae; Kim, J.C.; Bhuwalka, K.K.; Kim, D.H.; Kim, W.J.; Yoo, J.; Jeon, Hee-Kyung; Yang, Mikyung; Chung, Sang-Bong; Kim, D.; Ham, Boo-Hyun; Park, K.J.; Kim, W.D.; Park, S.H.; Song, Gyeong Ju; Kim, Y.H.; Kang, Myounggon; Hwang, Kyusung; Park, C.-H.; Lee, J.-H.; Kim, D.-W.; Jung, Sung Mi; Kang, Ho–Kyu

doi:10.1109/iedm.2018.8614629

Cited by 150 publications

(79 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Although FinFET has made enormous contributions to the IC industry since it was proposed in 1999 [ 16 ] and introduced into massive production in 2012 at the 22 nm technology node [ 17 ], it is difficult to meet the requirements of the performance and power consumption for further scaling down of device area. Gate-all-around (GAA) FET is a strong candidate for 3 nm technology, owing to its high performance and superiority in the control of SCEs [ 3 , 18 ]. In general, there are two kinds of GAAFETs, namely, horizontal GAAFET (hGAAFET) and vertical GAAFET (vGAAFET), depending on channel orientations.…”

Section: This Part Covers the Transistor Designs To The End Of Tecmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

View full text Add to dashboard Cite

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

show abstract

Section: This Part Covers the Transistor Designs To The End Of Tecmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

View full text Add to dashboard Cite

show abstract

“…Although the continuous scaling down of complementary metal oxide semiconductor (CMOS) devices, following Moore's Law in the past several decades, has enabled an amazing increase in transistor count and, hence, in the integrated functionality on a single chip 1 , the information explosion in the forthcoming IoT era requires more functionalities even allowed beyond Moore's Law 2,3 . However, modern CMOS devices have already evolved to sub-10 nm technology nodes 4,5 , accompanied by many unwanted effects 6 , such as short-channel effects, variability, etc., which make it very difficult for them to undergo further scaling. It is still unclear at this stage whether CMOS community can manage to sustain Moore's Law for the next 10 years.…”

Section: Introductionmentioning

confidence: 99%

A mode-balanced reconfigurable logic gate built in a van der Waals strata

et al. 2021

View full text Add to dashboard Cite

Two-dimensional (2D) semiconducting materials, in particular transition-metal dichalcogenides, have emerged as the preferred channel materials for sub-5 nm field-effect transistors (FETs). However, the lack of practical doping techniques for these materials poses a significant challenge to designing complementary logic gates containing both n- and p-type FETs. Although electrical tuning of the polarity of 2D-FETs can potentially circumvent this problem, such devices suffer from the lack of balanced n- and p-mode transistor performance, forming one of the most enigmatic challenges of the reconfigurable 2D-FET technology. Here we provide a solution to this dilemma by judicious use of van der Waals (vdW) materials consisting of conductors, dielectrics and semiconductors forming a 50 nm thin quantum engineered strata that can guarantee a purely vdW-type interlayer interaction, which faithfully preserves the mid-gap contact design and thereby achieves an intrinsically mode-balanced and fully reconfigurable all-2D logic gate. The intrinsically mode-balanced gate eliminates the need for transistor sizing and allows post-fabrication reconfigurability to the transistor operation mode, simultaneously allowing an ultra-compact footprint and increased circuit functionality, which can be potentially exploited to build more area-efficient and low-cost integrated electronics for the internet of things (IoT) paradigm.

show abstract

“…Therefore, as the device architecture becomes more complicated (in reality, multiple bridge channel field effect transistor (MBCFET), stacked nano-wire FET, stacked nano-slab FET, etc. for 3 nm CMOS technology node [8] and beyond), understanding the impact of LER on device performance is desperately required in developing variation-robust silicon device at 3 nm technology node and beyond [9]. A few studies have reported to understand, quantify, and analyze the impacts of LER on device characteristics [10] - [12].…”

Section: Introductionmentioning

confidence: 99%

Machine Learning (ML)-Based Model to Characterize the Line Edge Roughness (LER)-Induced Random Variation in FinFET

Lim

Shin

2020

IEEE Access

View full text Add to dashboard Cite

ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET). For a given LER features such as rms amplitude(Δ), correlation length along x-axis (ΛX), and correlation length along y-axis (ΛY), the metrics for device performance such as on-state drive current, off-state leakage current, threshold voltage, and subthreshold swing can be computing-efficiently estimated with the ANN model. INDEX TERMS Line edge roughness, process-induced random variation, FinFET, Machine Learning, Artificial neural network. Jaehyuk Lim, Changhwan Shin:ML-based model to characterize the LER induced random variation in FinFET Jaehyuk Lim, Changhwan Shin:ML-based model to characterize the LER induced random variation in FinFET VOLUME XX, 2020 9

show abstract

3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

Cited by 150 publications

References 0 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

A mode-balanced reconfigurable logic gate built in a van der Waals strata

Machine Learning (ML)-Based Model to Characterize the Line Edge Roughness (LER)-Induced Random Variation in FinFET

Contact Info

Product

Resources

About