3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer

Chang, Nistec; Chung, C. Key; Wang, Yu-Po; Lin, Chun-Tang; Su, PJ; Shih, Teny; Kao, Nicholas; Hung, Joe

doi:10.1109/ectc32862.2020.00295

Cited by 13 publications

(5 citation statements)

References 10 publications

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“…A significant difference in TDDB data between the two modes may indicate poor barrier characteristics. Therefore, it is essential to conduct these tests to ensure that the TSVs meet the desired reliability standards, and to improve the liner and barrier deposition technologies to achieve optimal performance [21,35,43].…”

Section: Copper Contaminationmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

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Section: Copper Contaminationmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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“…Chang et al [305] employed Cu/Sn-solder, Cu/Ni/Sn-solder, and Cu/Ni/Cu/Snsolder with a pitch <30 µm to investigate the stress distribution and IMCs at the TSV interface. Ni 3 Sn 4 was demonstrated to form at the solder-Ni-bump interface.…”

Section: Nanomodified Solder Bumpsmentioning

confidence: 99%

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

Jang,

Sharma,

Jung

2023

Materials

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Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

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“…The reliability of the solder bump is also affected by the TSV structure as the stress distribution by the formation of IMC at the interface. Chang et al [105] studied the stress simulation of the µ-bump structure stack up and metallic reaction for the 3D µ-bump interface in TSV. They adopted Cu-bump/Sn-solder (CS), Cu/Ni-bump/Sn-solder (CNS), and Cu/Ni/Cu-bump/Sn-solder (CNCS) with less than 30 um pitch.…”

Section: Reliability Of Solder Bump and Future Directionsmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer

Cited by 13 publications

References 10 publications

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

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