3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

Oh, Jin Kyung; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung Kyu; Lee, Hi‐Deok; Lee, Ga‐Won

doi:10.1016/j.sse.2013.04.004

Cited by 2 publications

(1 citation statement)

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“…In this work, four different high-k materials (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) were explored using the DQT model as these materials can be deposited on SiO 2 layer. [22][23][24] After these matters were clarified, the optimization was performed based on proposed method by Verma et al 14) For simplicity, the optimization was conducted using MOS capacitor (MOS-Cap) structure, in which to fairly assess the electrical behavior of the VARIOT combinations. The equivalent oxide thickness (EOT) of asymmetric VARIOT is fixed for 4 : 1 : 8 nm while varying its low-k thickness, Tox from 1 nm to the corresponding EOT.…”

Section: Simulation Proceduresmentioning

confidence: 99%

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

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