3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

Abstract

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>

Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

“…The quest for smaller transistors centers on nanoscale technology, which drives major breakthroughs in semiconductors [1][2][3][4][5][6][7], by enabling hundreds of circuits on a chip through Very Large Scale and Ultra-Large Scale Integrations. However, reducing device dimensions generate short channel effects, (SCEs) [8][9][10][11][12][13][14] in single gate MOSFETs, which negatively influence current and cause off-state leakage. To address these challenges, FinFETs stand out as prospective electronic devices [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] due to their improved scalability and ability to control SCEs.…”

Analysis of analog and RF behaviors in junctionless double gate vertical MOSFET

“…As the transistor's size shrinks drastically towards sub-nanometer regime, the threshold voltage (VTH) would be rolled-off along with the decreasing channel length (Lch), which eventually deteriorating the overall performance due to short channel effects (SCE) [10]. Th e most difficult challenge in transistor's miniaturization is to form ultra -shallow source/drain (S/D) junctions with high doping gradient which requires advanced source/drain and channel engineering processes [11,12]. For that reason, a lot of alternative device structures have emerged for realizing the Moore's law prediction without degrading the transistor performances.…”

New voltage and temperature scalable gate delay model applied to a 14nm technology

“…This methodology is CMOS technology independent as the physical variation of delay is not supposed to vary with technology.However, the results presented in this paper are results of simulations done on cells developped on a finFET 14nm node. The finFET transitor has been introduced as an alternative to the planar CMOS in order to fulfill Moore's law and has the advantage of minimizing the impact of short channel effects [19][20][21].…”