34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

Satpathy, Sudhir; Mathew, Sanu; Suresh, Vikram; Gopal, Vinodh; Guilford, James; Anders, Mark; Kaul, Himanshu; Agarwal, Amit; Hsu, Steven; Krisnnamurthy, Kam

doi:10.1109/esscirc.2018.8494238

Cited by 6 publications

(2 citation statements)

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“…In [ 11 , 28 , 29 , 30 ], the designs of hardware accelerators for decompression were proposed. Koch et al [ 11 ] presented hardware decompression techniques for embedded systems.…”

Section: Related Workmentioning

confidence: 99%

“…The decoder is implemented on FPGA with an embedded microprocessor. Satpathy et al [ 29 ] presented a decompression accelerator that applies a dual-arithmetic logic unit (ALU) architecture and block-adaptive Huffman decoder. The dual-ALU is utilized to improve the serial bottleneck of Huffman decoding by matching the Huffman code with two additional arrays.…”

Section: Related Workmentioning

confidence: 99%

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Lossless Decompression Accelerator for Embedded Processor with GUI

Hwang

Cho

et al. 2021

Micromachines

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The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

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“…In [ 11 , 28 , 29 , 30 ], the designs of hardware accelerators for decompression were proposed. Koch et al [ 11 ] presented hardware decompression techniques for embedded systems.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%