3-D AND-Type Flash Memory Architecture With High-κ Gate Dielectric for High-Density Synaptic Devices

Seo, Young-Tak; Kwon, Dongseok; Noh, Yoohyun; Soo-Chang, Lee; Park, Minkyu; Woo, Sung Yun; Park, Byung‐Gook; Lee, Jong-Ho

doi:10.1109/ted.2021.3089450

Cited by 18 publications

(10 citation statements)

References 21 publications

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“…The flash cells are configured in an ANDtype array architecture, in which source lines and drain lines are parallel. The AND-type array has the advantages of low-power selective write operations, scalability, and large-scale parallel computing (41)(42)(43). On the other hand, selective write operations in a NOR-type array consume a lot of energy, and it is difficult to perform large-scale parallel operations in a NAND-type array due to a cell string structure.…”

Section: Device Characterizationmentioning

confidence: 99%

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

et al. 2023

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Neuromorphic computing (NC) architecture inspired by biological nervous systems has been actively studied to overcome the limitations of conventional von Neumann architectures. In this work, we propose a reconfigurable NC block using a flash-type synapse array, emerging positive feedback (PF) neuron devices, and CMOS peripheral circuits, and integrate them on the same substrate to experimentally demonstrate the operations of the proposed NC block. Conductance modulation in the flash memory enables the NC block to be easily calibrated for output signals. In addition, the proposed NC block uses a reduced number of devices for analog-to-digital conversions due to the super-steep switching characteristics of the PF neuron device, substantially reducing the area overhead of NC block. Our NC block shows high energy efficiency (37.9 TOPS/W) with high accuracy for CIFAR-10 image classification (91.80%), outperforming prior works. This work shows the high engineering potential of integrating synapses and neurons in terms of system efficiency and high performance.

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Section: Device Characterizationmentioning

confidence: 99%

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

et al. 2023

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“…Unlike software-based weight initialization, the synaptic devices can only have limited number of conductance values (weights). More recently, the synaptic devices are realized by a single memory device including chargetrap flash (CTF) memory [16], resistive-switching randomaccess memory (RRAM) [6,[17][18][19][20], phase-change randomaccess memory (PRAM) [21], ferroelectric random-access memory (FRAM) [22], and magnetic random-access memory (MRAM) [23] for increasing the synapse array density and minimizing the power consumption, departing from the conventional synapses made up of circuits or several electron devices. Also, many of today's state-of-the-art deep learning models such as Inception v1, VGG-19, ResNet, and others contain huge number of neurons with millions of parameters [24][25][26][27].…”

Section: Motivationmentioning

confidence: 99%

“…The activation matrix is given by the matrix K such that K ∈ R M×n .The rows of K can be considered as M data points in an n dimensional space since K is an M × n matrix. From a hardware perspective, realization of such an SLFN would require synaptic devices like resistive-switching randomaccess memory [17], charge-trap flash memory [16], fieldeffect transistor [39], phase-change memory [21] for the storage of weight values cooperating with CMOS neuron circuits [40,41]. Essentially, the synaptic devices utilize their electrical conductance states as the equivalent weight values and the neuron circuits are operated based on the behavior of the activation function.…”

Section: Mathematical Preliminariesmentioning

confidence: 99%

Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application

2022

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This work focuses on the optimization of the structural complexity of a single-layer feedforward neural network (SLFN) for neuromorphic hardware implementation. The singular value decomposition (SVD) method is used for the determination of the effective number of neurons in the hidden layer for Modified National Institute of Standards and Technology (MNIST) dataset classification. The proposed method is also verified on a SLFN using weights derived from a synaptic transistor device. The effectiveness of this methodology in estimating the reduced number of neurons in the hidden layer makes this method highly useful in optimizing complex neural network architectures for their hardware realization.

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“…However, there is a drawback that an error occurs in the current summation due to a problem such as sneak current, which requires additional active selecting components and results in one-selectorone-resistor (1S-1R) or one-transistor-one-resistor (1T-1R) array structures. [30][31][32][33][34] In contrast, transistor-type synaptic devices are free from these issues thanks to the gate electrode, [35][36][37][38] and these devices are typically integrated in NAND or NOR array structures. NOR-type structure offers the advantage of parallel matrix operations, similar to artificial neural networks (ANNs), but requires individual drain contacts for each cell, resulting in an area inefficiency of over 10F 2 .…”

Section: Introductionmentioning

confidence: 99%

Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing

Hwang,

Yu,

Song

et al. 2023

Advanced Science

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The progress of artificial intelligence and the development of large‐scale neural networks have significantly increased computational costs and energy consumption. To address these challenges, researchers are exploring low‐power neural network implementation approaches and neuromorphic computing systems are being highlighted as potential candidates. Specifically, the development of high‐density and reliable synaptic devices, which are the key elements of neuromorphic systems, is of particular interest. In this study, an 8 × 16 memcapacitor crossbar array that combines the technological maturity of flash cells with the advantages of NAND flash array structure is presented. The analog properties of the array with high reliability are experimentally demonstrated, and vector‐matrix multiplication with extremely low error is successfully performed. Additionally, with the capability of weight fine‐tuning characteristics, a spiking neural network for CIFAR‐10 classification via off‐chip learning at the wafer level is implemented. These experimental results demonstrate a high level of accuracy of 92.11%, with less than a 1.13% difference compared to software‐based neural networks (93.24%).

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3-D AND-Type Flash Memory Architecture With High-κ Gate Dielectric for High-Density Synaptic Devices

Cited by 18 publications

References 21 publications

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application

Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing

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