Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

Abstract

Neuromorphic computing (NC) architecture inspired by biological nervous systems has been actively studied to overcome the limitations of conventional von Neumann architectures. In this work, we propose a reconfigurable NC block using a flash-type synapse array, emerging positive feedback (PF) neuron devices, and CMOS peripheral circuits, and integrate them on the same substrate to experimentally demonstrate the operations of the proposed NC block. Conductance modulation in the flash memory enables the NC block to be easily calibrated for output signals. In addition, the proposed NC block uses a reduced number of devices for analog-to-digital conversions due to the super-steep switching characteristics of the PF neuron device, substantially reducing the area overhead of NC block. Our NC block shows high energy efficiency (37.9 TOPS/W) with high accuracy for CIFAR-10 image classification (91.80%), outperforming prior works. This work shows the high engineering potential of integrating synapses and neurons in terms of system efficiency and high performance.

Domain wall magnetic tunnel junction-based artificial synapses and neurons for all-spin neuromorphic hardware

“…The integration of NVMs and CMOS electronics provides benefits such as nonvolatility, scalability, direct mapping of synaptic weights, as well as facilitating functions such as data thresholding, conversion, and trimming required for each layer of a neuromorphic DNN 7 , 13 – 18 . There are typical reports on the realization of operations in DNNs using different types of NVMs, such as resistive random-access memory (RRAM) 19 , 20 , phase change memory (PCM) 21 , ferroelectric RAM (FeRAM) 22 , flash memory 23 , and magnetic RAM (MRAM) 24 . While these NVMs show promise for neural network applications, they also come with inherent challenges related to nonlinearity, energy efficiency, area overhead, and reliability 3 .…”

Multilevel Ferroelectric Domain Wall Memory for Neuromorphic Computing

“…[3][4][5][6][7] Ideally, a delay-less and energy-efficiency in-memory computing can avoid data-shuttling between the DOI: 10.1002/adfm.202315954 separated processor and the memory, [8][9][10][11] enabling the execution of high-efficiency and in-parallel matrix-vector multiplications (MVM) which is commonly performed in a convolutional neural network (CNN) for image-processing-related tasks. [12][13][14][15][16] There are many emerging memories available for computing, including ferroelectric memories, phase-change memories, resistive memories, magnetoresistive memories, etc., [17][18][19][20][21] among which ferroelectric memories are classified as a 1T1C structured ferroelectric random access memory (FeRAM), a metalferroelectric-insulator-metal structured ferroelectric field-effect transistor (FeFET), and a ferroelectric domain wall memory (DWRAM) relying on high conductivity of erasable ferroelectric domain walls. [22][23][24][25] In comparison, the FeRAM depends a destructive readout process of charge integration resulting in a lower storage density, [26] and the FeFET suffers from the poor polarization retention due to the chemical reaction at the interface between the ferroelectric layer and the underlying semiconductor channel, leading to a significant leakage current and polarization fatigue.…”