23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Ha, Kwang Soon; Lee, Chang-Kyo; Lee, Dongkeon; Jang, Jae Hoon; Hwang, Hee-Chul; Chi, Hyung-Joon; Park, Jung Hwan; Shin, Seung‐Jun; Park, Dukha; Kim, Sang-Yun; Lim, Soon Kwon; Park, Kiwon; Choi, YeonKyu; Kim, Young-Hwa; Son, Younghoon; Cho, Hyunyoon; Na, Byongwook; Ahn, Hyo-Joo; Lee, Seungseob; Choi, Seouk-Kyu; Park, Youn-sik; Hyun, Seok-Hun; Chang, Seunghyuk; Kwon, Hyeokshin; Choi, Jung-Hwan; Oh, Taehyoun; Sohn, Young-Soo; Park, Kwang-II; Jang, Seong-Jin

doi:10.1109/isscc.2019.8662509

Cited by 15 publications

(2 citation statements)

References 5 publications

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“…The rapid increase in IP traffic in data centers is driving the demand for high-speed and low-power memory interfaces [1], [2]. There is limited scope to increase the bandwidth of present memory interfaces, which use non-return-to-zero (NRZ) signaling, because of channel losses as the data-rate increases [3], [4].…”

Section: Introductionmentioning

confidence: 99%

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

2022

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Separate inverter-based summers for each eye are introduced into the decision feedback equalizer (DFE) of a single-ended four-level amplitude modulation (PAM-4) receiver for memory interfaces. The summers increase the input swing of the slicers while maintaining the advantages of inverter-based amplifiers with higher gain and lower power consumption than current-mode logic (CML) amplifiers. The high-gain summer can improve clock-to-Q delays of slicers in the PAM-4 DFE without increasing the power consumption of the slicers. This can alleviate the timing constraint that the DFE must meet to respond correctly to the previous data. The non-linear gain of the inverter-based structure can be ignored by using separate paths depending on each eye. A prototype chip was fabricated in a 65 nm CMOS process. At 24 Gb/s, the DFE can achieve a bit error rate (BER) of 10 -12 with an eye width of 100 mUI with -7.3 dB insertion loss at Nyquist frequency and the power efficiency of 0.73 pJ/b.INDEX TERMS Four-level pulse amplitude modulation (PAM-4) receiver, inverter-based summer, memory interface

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Section: Introductionmentioning

confidence: 99%

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

2022

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“…As the amount of data handled in memory increases, the memory interface is evolving to allow high-speed operation with high energy efficiency [1,2]. With this trend, increasing data-rate and clock frequency is required but this is limited by low-performance DRAM process [3].…”

Section: Introductionmentioning

confidence: 99%

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces

Park

Lee

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a quadrature signal corrector (QSC) with high accuracy and fast correction for memory interfaces is presented. An adaptive delay gain controller in the QSC adjusts each delay gain of four digitally controlled delay lines (DCDLs) separately depending on skew between the quadrature clocks, resulting in short correction time together with low residual skew. To validate the effectiveness of our QSC in memory interfaces, a quarter-rate single-ended 1-tap decision feedback equalizer (DFE) with the QSC was fabricated in a 65nm CMOS process. Using the adaptive delay gain controller, the QSC reduced the skew between the 3 GHz quadrature clocks from a maximum of 21.2 ps to 0.8 ps while correction time was reduced by a factor of 3.9 compared to that without using the adaptive delay gain controller. At 12 Gb/s, the DFE using our QSC achieved a BER of 10 −12 with an eye width of 140 mUI when the input clock skew is 13.2 ps.

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A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

Jin

Byun

Cho

et al. 2021

2021 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Cited by 15 publications

References 5 publications

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces

A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

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