A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

Jin, Hyungmin; Byun, Joonho; Cho, Hyunyoon; Yoon, Hee-Sun; Park, Jin Hee; Kim, Kyoung-Soo; Choi, Yong‐Sang; Choi, Jung-Hwan; Ko, Hyung–Jong; Lee, Sang‐Hyun

doi:10.1109/a-sscc53895.2021.9634750

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A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

Cited by 6 publications

References 4 publications

A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test

A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test

A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation

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