A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge

Yun, Daeho; Park, Minsu; Kim, Kahyun; Baek, Kyungmin; Lee, Eonhui; Choi, Woo-Seok; Jeong, Deog-Kyoon

doi:10.1109/a-sscc58667.2023.10347967

2023 IEEE Asian Solid-State Circuits Conference (A-Sscc) 2023

DOI: 10.1109/a-sscc58667.2023.10347967

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A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge

Daeho Yun,

Minsu Park,

Kahyun Kim

et al.

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A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge

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