A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a lowresolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC . A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply and achieves 5.2 ENOB Nyq with a background offset calibration.I. 978-1-4799-0280-4/13/$31.00 c 2013 IEEE
This paper proposes a replica-driving technique that can be applied to implement low-power high-performance switched-capacitor (SC) amplifiers. The reduced swing range problem arising from the output-stage source-follower is resolved by a simple SC level shifter, without additional supply or static buffer. The output driving capability is enhanced by using a capacitivelycontrolled class-AB output stage. Owing to the high-speed openloop output driving, the reference driver does not require any bypass capacitor. A prototype 12 bit 150 MS/s pipelined ADC was designed for concept proof in a 65 nm CMOS process. The ADC core consumes 75.6 mW at a 1.2 V supply. The measured DNL and INL are 0.5 LSB and 1.5 LSB, respectively. The SNDR and SFDR are 58.2 dB and 73.6 dB at 150 MS/s with an 8.3 MHz input.Index Terms-Pipelined ADC, replica driving, switchedcapacitor (SC) amplifier.
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