A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a lowresolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC . A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply and achieves 5.2 ENOB Nyq with a background offset calibration.I. 978-1-4799-0280-4/13/$31.00 c 2013 IEEE
A 7 bit 2 GS/s flash ADC fabricated in a 65nm CMOS process is presented. The proposed cascaded latch interpolation technique achieves a 4 interpolation factor with only dynamic comparators. A background latching-time adjustment scheme utilizing a replica latch array ensures an interpolation capability that is robust to process, voltage and temperature variations. The measured peak INL and DNL of 0.64 LSB and 0.58 LSB, respectively, after comparator offset calibration prove successful interpolation operation. The measured SNDR and SFDR were 38.12 dB and 49.05 dB, respectively, with a 1.08GHz input at 2 GS/s operation while consuming 20.7 mW of total power. This ADC achieves a figure of merit of 157 fJ/conversion-step with a Nyquist input at 2 GS/s.
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