17 GHz transceiver design in 0.13 μm CMOS

Abstract

This paper presents the research work towards a fully integrated 17 GHz transceiver in 0.13 prn standard CMOS. The simultaneous challenge of high-integration, highest frequency and low-voltage design is solved cornbining optimized on-chip passives and RF circuit techniques with a double-conversion sliding RF-architecture. Three measured chips clearly demonstrate the 'feasibility of a CMOS transceiver at highest frequency. A fully integrated A -C 13 GHz PLL consumes GO mW from 1.5 V supply. The complete RF RX-path features a gain of 37dB, IIPJ of -37dBm and a SSB NF of 9.3dB, consuming l8O.81nW from 1.5V supply. A first T X path testchip includes the second modulator and linear output driver. Consuming 93mW from 2.5V supply, it features a gain of 4dB and an OIP3 of I3dBm.

Design of a double balanced square law CMOS up-conversion mixer with improved input isolation technique for high frequency applications

“…Gilbert mixer is probably the most popular choice, but is usually power hungry. For example, 40.5mW and 93mW power consumptions are reported in [8] and [9] respectively. Folded mixers are familiar for their better linearity, but are noisy.…”