Geometry Optimization of Sub-100nm Node RF CMOS Utilizing Three Dimensional TCAD Simulation

Tatsumi, Tetsuya

doi:10.1109/essder.2006.307702

Cited by 6 publications

(1 citation statement)

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“…As device scaling down, the impact of finger length on high-frequency characteristics has been discussed [4], [5]. Tatsumi [6] and A. Nakamura et al [7] also proposed the layout optimization of MOSFETs by TCAD simulations. Recently, a new layout design using 90-nm CMOS process was proposed to realize millimeter-wave circuits [8].…”

Section: Introductionmentioning

confidence: 98%

Wiring Effect Optimization in 65-nm Low-Power NMOS

Chan

Chen

Tsai

et al. 2008

IEEE Electron Device Lett.

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This letter investigates the wiring effect on RF performance in advanced 65-nm low-power CMOS technology. New designs are proposed to minimize the parasitic resistances and capacitances associated with the interconnects in the transistor. Compared with the standard multifinger devices provided by the foundry, the device with the optimized wiring parasitic capacitances and resistances presents improvement up to ∼21% for f T (increased from 89 to 108 GHz) and ∼22% for f max (increased from 130 to 159 GHz), respectively. The extracted equivalent circuit model parameters indicate that the proposed approach can effectively minimize the parasitic effects leading to improved RF performance of the advanced MOSFETs.

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