13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

Hamzaoglu, Fatih; Arslan, Ümüt; Bisnik, Nabhendra; Ghosh, Swaroop; Lal, Manoj B.; Lindert, N.; Meterelliyoz, Mesut; Osborne, Randy B.; Park, Joodong; Tomishima, Shigeki; Wang, Yih; Zhang, Kevin

doi:10.1109/isscc.2014.6757412

Cited by 35 publications

(8 citation statements)

References 4 publications

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“…Together with the selector, extra circuitry is required to sense and discriminate the memory states. eDRAM peripheral circuitry typically consumes around 50% (overhead surface percentage, A Over ) of the total available surface [14]. Figure 9 shows a) a simplified layout and b) electric diagram of a 2x2 Z 2 -FET memory matrix.…”

Section: Edram Density Integration Comparisonmentioning

confidence: 99%

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Navarro

Duan

Parihar

et al. 2017

IEEE Trans. Electron Devices

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Abstract-2D numerical simulations are used to demonstrate the Z 2 -FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

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Section: Edram Density Integration Comparisonmentioning

confidence: 99%

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Navarro

Duan

Parihar

et al. 2017

IEEE Trans. Electron Devices

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“…Designing a novel architecture to achieve the goal in the target region in Figure 1 is challenging. It is dicult to keep adding more memories to processors, since even the high-density eDRAM suffers from a much larger cell size (60F 2 80F 2 [31,38]) than DRAMs (6F 2 ). On the other hand, it is also dicult to improve PIM's performance.…”

Section: Compute-capable Memory (Pim)mentioning

confidence: 99%

Drisa

Niu

Malladi

et al. 2017

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture

250

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Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the rst one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite. To address the challenge, we propose DRISA, a DRAM-based Recongurable I n-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be recongured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate signicant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8⇥ speedup and 1.2⇥ better energy eciency compared with ASICs, and 7.7⇥ speedup and 15⇥ better energy eciency over GPUs with integer operations.

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“…When render failure happens, the user will see blurred or blank tiles. The memory wall has been a known problem and Intel presented Crystalwell (128MB eDRAM cache for Haswell) [12]. AnandTech measured the memory latency with and without Crystalwell (Fig.…”

Section: A Smooth Graphicsmentioning

confidence: 99%

System design challenges for future consumer devices: From glass to Chromebooks

Shiu

2016

2016 International Conference on Electronics Packaging (ICEP)

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Internet and mobile application have been the driving force for semiconductor innovation in the past 10 years. In this paper, we will focus on the system design challenges for today's and tomorrow's consumer gadgets from productivity laptop computers to wearable glasses. We will start with everyone's favorite apps such as finding the fastest route to a baseball game with Google maps, taking family pictures and sharing with Google photos, watching TV shows on YouTube, calling grandparents with Hangouts, writing a research paper with Google Doc/Drive. We will break these activities into various system requirements for the software application developers, system architects, technologists and hardware engineers. The design challenges often result from the laws of physics such as the memory latency and thermal management or the law of economics such as cost and time to market. We will describe areas where hardware and software communities can work together to deliver the ultimate user satisfaction. Finally, a few future research areas in memory architecture, package technology and circuit design will be discussed.

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13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

Cited by 35 publications

References 4 publications

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Drisa

System design challenges for future consumer devices: From glass to Chromebooks

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