Drisa

Abstract

Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the rst one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite. To address the challenge, we propose DRISA, a DRAM-based Recongurable I n-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be recongured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate signicant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8⇥ speedup and 1.2⇥ better energy eciency compared with ASICs, and 7.7⇥ speedup and 15⇥ better energy eciency over GPUs with integer operations.

Functional Applications of Future Data Storage Devices

“…An insitu accelerator DRISA with large internal memory bandwidth and high computing performance was proposed to address this problem. [22] Experimental results showed that DRISA achieved significant performance improvement in convolutional neural network inference acceleration compared to state-of-the-art systems (ASICs and GPUs).…”

“…The memory cell stores digital binary values represented by the retained charge or device resistance. [21][22][23] By configuring the reference voltage (V ref ) of SAs, different Boolean functions can be implemented. This operating scheme is not a fully inmemory computation to a certain extent, as it requires the cooperation of peripheral circuits to convert the computing results.…”

“…A typical operating scheme is to perform logic operation in the memory array (Figure3m), in which the data stored in memory cells of the selected rows and columns is calculated on bit lines (BLs) through charge sharing or current summation, and the final results are output through external sensing amplifiers (SAs) and written back to the memory array if necessary. The memory cell stores digital binary values represented by the retained charge or device resistance [21][22][23]. By configuring the reference voltage (V ref ) of SAs, different Boolean functions…”

Logic‐In‐Memory Characteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure

“…[6][7][8][9][10][11] LIM comprising SRAM or DRAM arrays has demonstrated relatively high reliability, high computation speed, and low operating voltage compared to RRAM-or MRAM-based LIM. [12][13][14][15][16] Recently, feedback field-effect transistors (FBFETs) that operate via positive feedback (PF) loop mechanisms have attracted DOI: 10.1002/aelm.202300132 attention for LIM. [17][18][19][20] PF loops are generated or eliminated in the channels because of the recursive mutual interaction between the carrier injection and potential barriers.…”

“…[1][2][3][4][5]33] Various memory devices, including resistive random-access memory (RRAM), magnetoresistive RAM (MRAM), static RAM (SRAM), and dynamic RAM (DRAM), have been widely researched for developing LIM. [5][6][7][8][9][10][11][12][13][14][15][16] Particularly, LIM composed of RRAM or MRAM has performed stateful logic operations via voltage division between the devices and resistors. [6][7][8][9][10][11] LIM comprising SRAM or DRAM arrays has demonstrated relatively high reliability, high computation speed, and low operating voltage compared to RRAM-or MRAM-based LIM.…”