12-Channel &amp;#x00D7; 20-Gbps on-board parallel optical modules using multi-chip visual alignment technique

Sugimoto, T.; Hashimoto, Y.; Yamamoto, Keisuke; Kurihara, Minoru; Oda, Mikio; Sakai, Jun; Ono, Hiroshi; Akagawa, Takeshi; Yashiki, Kenichiro; Hatayama, H.; Suzuki, Nobuhiro; Tsuji, Masayoshi; Ogura, I.; Kouta, Hikaru; Kurata, K.

doi:10.1109/ectc.2010.5490963

Cited by 5 publications

(3 citation statements)

References 2 publications

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“…This leads to high precision steps which need to be optimized for the application and cannot take advantage of the economies of scale available to most electronic components. There has been work on passive alignment techniques [4], but the need for mirrors or lenses to couple the power from devices to the fiber/waveguide adds to the overall cost. To ensure that links can be available at reasonable cost, three main technologies have been employed in the assembly of this proposed hybrid interconnect: planar butt-coupled optical alignment, passive alignment to the waveguide, and a flexible substrate.…”

Section: Planar Assemblymentioning

confidence: 99%

Planar assembled flexible interconnect link with hybrid optical/electrical data transmission for mobile device applications

Keller¹,

Shao²,

Wakazono³

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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New serial data transmission standards for cameras and displays in mobile devices are demanding low power multigigabit high speed serial links which must operate in noisy RF environments.[1] To meet these requirements a hybrid optical/electrical interconnect link is proposed. By combining a traditional flexible electrical interconnect with an advanced low power optical interconnect it is possible to meet the demands of this future market. The two key developments discussed in this paper are: the electrical/optical switching system, which is the basis for the hybrid link, and the all planar assembly process, featuring an edge emitting laser diode, edge receiving photodiode and a flexible polymer waveguide.

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Section: Planar Assemblymentioning

confidence: 99%

Planar assembled flexible interconnect link with hybrid optical/electrical data transmission for mobile device applications

Keller¹,

Shao²,

Wakazono³

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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“…This article describes the design of 4 × 25 Gb/s parallel optical receiver analog front‐end (AFE) for 100 Gb/s Ethernet application. Applying four channels in parallel can decrease the transmission rates of each channel and alleviate the difficulties related to technology, speed, and cost .…”

Section: Introductionmentioning

confidence: 99%

4 × 25 Gb/s 2.6 mW/Gb/s parallel optical receiver analog front‐end for 100 Gb/s Ethernet

Chen

Luo

et al. 2015

Micro & Optical Tech Letters

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A design of 4 × 25 Gb/s parallel optical receiver analog front‐end, including transimpedance amplifier (TIA) and limiting amplifier (LA), is presented in this article. It features a pseudodifferential TIA structure to cancel common mode noise and stabilize circuit. The TIA and LA use regulated cascode technique and four stages interleaving active feedback structure to acquire 23.2 GHz bandwidth and 74.3 dBΩ transimpedance gain. The parallel TIA and LA chip occupies 525 × 1835 μm2 area. It consumes 76 mW per channel and the power consumption per bit is only 2.6 mW/Gb/s. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:974–978, 2015

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“…Vertical cavity surface emitting lasers (VCSELs) have become the preferred light source for the parallel optical transmission, due to their low cost, small volume, low power consumption and high modulation bandwidth [1]. A VCSEL array should be driven by a parallel laser diode driver (LDD) chip, which enlarges the high‐speed signal from a multiplexer and turns the laser diode on, converting electronic signals to optical signals.…”

Section: Introductionmentioning

confidence: 99%

4‐channel 35 Gbit/s parallel CMOS LDD

et al. 2015

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The design of a 4-channel 35 Gbit/s parallel laser diode driver (LDD) using 65 nm CMOS technology is presented. The LDD driver consists of an input buffer stage, a pre-amplifier stage and an output driver stage. The three-stage cascaded amplifiers constitute the pre-amplifier stage, and an active feedback technique is employed to expand bandwidth without consuming a large area. The output driver stage introduces RC negative feedback and inductive shunt peaking techniques to broaden the bandwidth. Measurement results show that the operating rate of each channel is up to 35 Gbit/s and the power consumption per data rate is only 4.4 mW/(Gbit/s).

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12-Channel × 20-Gbps on-board parallel optical modules using multi-chip visual alignment technique

Cited by 5 publications

References 2 publications

Planar assembled flexible interconnect link with hybrid optical/electrical data transmission for mobile device applications

Planar assembled flexible interconnect link with hybrid optical/electrical data transmission for mobile device applications

4 × 25 Gb/s 2.6 mW/Gb/s parallel optical receiver analog front‐end for 100 Gb/s Ethernet

4‐channel 35 Gbit/s parallel CMOS LDD

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