4‐channel 35 Gbit/s parallel CMOS LDD

Abstract

The design of a 4-channel 35 Gbit/s parallel laser diode driver (LDD) using 65 nm CMOS technology is presented. The LDD driver consists of an input buffer stage, a pre-amplifier stage and an output driver stage. The three-stage cascaded amplifiers constitute the pre-amplifier stage, and an active feedback technique is employed to expand bandwidth without consuming a large area. The output driver stage introduces RC negative feedback and inductive shunt peaking techniques to broaden the bandwidth. Measurement results show that the operating rate of each channel is up to 35 Gbit/s and the power consumption per data rate is only 4.4 mW/(Gbit/s).

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

“…Transistors can be stacked to reach multiples of breakdown voltages. This is a technique common for drivers in CMOS such as [22], [23], or [24]. However, this technique is sensitive to start-up sequences and might breakdown on transient peaks.…”

4-channel, 224Gb/s PAM-4 optical transmitter with group delay compensation in 130-nm BiCMOS technology

“…Driven by the proliferating operating-rate demand of Internet traffic, optical connection using the vertical-cavity surface-emitting laser (VCSEL) and non-return to zero binary amplitude shift keying (NRZ-OOK) modulation method is commercialized in [1][2][3][4][5][6][7][8][9]. From the perspective of low power, low cost, and high integration, the CMOS technology was adopted in [1][2][3][4]. Meanwhile, [5][6][7][8][9] achieved higher operating rates through the use of SiGe BICMOS technology, with less jitter and higher modulation current.…”