4 × 25 Gb/s 2.6 mW/Gb/s parallel optical receiver analog front‐end for 100 Gb/s Ethernet

Chen, Yingmei; Luo, Xianliang; He, Xiaofei; Zhang, Yunan; Wang, Pengxia

doi:10.1002/mop.28996

Cited by 8 publications

(6 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is necessary to use an output buffer with the large tail current to drive the load capacitance and provide output swing for measurements and practical applications [14,29]. However, the large parasitic capacitances of the output buffer will deteriorate the bandwidth of Rx_AFE.…”

Section: Double ƒ T Buffermentioning

confidence: 99%

“…Nevertheless, many bandwidth extension techniques cannot produce a marked effect because of the scale-down supply voltage. For example, the regulated cascade circuit (RGC) TIA has exhibited superior bandwidth performance due to the low input impedance [14][15][16]. However, owing to the low supply voltage, the main advantages of the RGC TIA is seriously suppressed by the limited gain of the feedback amplifier [17,18].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

Zhou

Mao

Xie

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

In this paper, a 30 Gbps 1.25 pJ/b optical receiver analog front-end (Rx_AFE) mainly consisting of an active voltage-current feedback transimpedance amplifier (AVCF-TIA) and a staggered active feedback limiting amplifier (LA) is presented. By adopting active voltage-current feedback technique in the proposed TIA, the large input capacitance is well-isolated without the limitation of low supply voltage, and the direct contradiction between transimpedance gain and output pole frequency is alleviated significantly. Meanwhile, the bandwidth is further extended by adopting staggered active feedback technique in the LA designing. Fabricated in a 40 nm bulk-CMOS technology, the presented Rx_AFE exhibits a transimpedance gain of 63.8 dBΩ and a 3-dB bandwidth of 24.3 GHz. From supply voltage of 1.0 V, power dissipation and power efficiency of the circuit are 37.5 mW and 1.25 pJ/b respectively, when 30 Gbps PRBS is operated. The core circuit occupies a chip area of 920 µm × 690 µm.

show abstract

Section: Double ƒ T Buffermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

Zhou

Mao

Xie

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The output buffer of the front‐end amplifier employs double f T technique to expand the bandwidth [5]. For increasing the output swing and reducing high frequency reflection, the load resistors of the output buffer are compromised on 75 Ω.…”

Section: Afe Architecturementioning

confidence: 99%

12‐Channel, 480 Gbit/s optical receiver analogue front‐end in 0.13 μm BiCMOS technology

Chen

Zhang

et al. 2017

Electron. lett.

Self Cite

View full text Add to dashboard Cite

A compact 12-channel 480 Gbit/s optical receiver analogue front-end (AFE) for parallel optical transmission systems has been implemented in 0.13 μm SiGe BiCMOS technology. The transimpedance amplifier of AFE employed common-gate amplifier and negative feedback structure to decrease input impedance and broaden bandwidth. The limiting amplifier adopted modified Cherry-Hooper amplifier with active feedback technique to stabilise current and acquire high gain simultaneously. Without on-chip spiral inductors, the spacing of adjacent channels is constricted to 250 μm and the chip area is only 3350 × 700 μm. With the psuedo-random binary sequence (PRBS) input data, the maximum operating rate of the AFE is 38.7 Gbit/s; meanwhile, the root mean square (RMS) jitter is 2.16 ps and the single-ended output amplitude of 183.7 mV is achieved. The power consumption of each channel is 150 mW from a 3.3 V supply.

show abstract

“…Trans-impedance amplifiers (TIAs) are key circuits in current optoelectronic communication systems [5]- [33]. In particular, efficient solutions for Ethernet beyond 5G have been presented (InP heterojunction bipolar transistor (HBT) process design [27] and CMOS designs [18], [19], [22], [23], [26], [30], [32], [33]). From the costeffectiveness perspective of CPO implementation, smallarea and low-power CMOS TIA is very attractive for highspeed Rx analog front-end (Rx-AFE).…”

Section: Introductionmentioning

confidence: 99%

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process

Takahashi

Ito

Nakamura

et al. 2023

IEICE Electron. Express

View full text Add to dashboard Cite

We present an area-efficient and low-power four-channel 25-Gb/s trans-impedance amplifier for an Rx analog front-end (Rx-AFE) on an optical receiver. The proposed circuit features a local negative-feedback trans-impedance amplifier (TIA) to expand the bandwidth. The TIA and post-amplifier use regulated cascode (RGC) topology and two differential amplifier stages with an inductive peaking bandwidth extension technique to acquire 19.6 GHz of the −3 dB bandwidth and 53.3 dBΩ of the gain. We designed the system using a 65-nm CMOS process, and the proposed four-channel Rx-AFE TIAs achieved a small area of 300 𝜇m × 800 𝜇m per lane. From the measurement results, the differential output voltage was 160 mV at 25-Gb/s PRBS31. The test chip has also 85.0 mW of power consumption; hence, it achieves 0.85 mW/Gb/s of power efficiency.

show abstract

4 × 25 Gb/s 2.6 mW/Gb/s parallel optical receiver analog front‐end for 100 Gb/s Ethernet

Cited by 8 publications

References 9 publications

A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

12‐Channel, 480 Gbit/s optical receiver analogue front‐end in 0.13 μm BiCMOS technology

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process

Contact Info

Product

Resources

About