12‐Channel, 480 Gbit/s optical receiver analogue front‐end in 0.13 μm BiCMOS technology

Abstract

A compact 12-channel 480 Gbit/s optical receiver analogue front-end (AFE) for parallel optical transmission systems has been implemented in 0.13 μm SiGe BiCMOS technology. The transimpedance amplifier of AFE employed common-gate amplifier and negative feedback structure to decrease input impedance and broaden bandwidth. The limiting amplifier adopted modified Cherry-Hooper amplifier with active feedback technique to stabilise current and acquire high gain simultaneously. Without on-chip spiral inductors, the spacing of adjacent channels is constricted to 250 μm and the chip area is only 3350 × 700 μm. With the psuedo-random binary sequence (PRBS) input data, the maximum operating rate of the AFE is 38.7 Gbit/s; meanwhile, the root mean square (RMS) jitter is 2.16 ps and the single-ended output amplitude of 183.7 mV is achieved. The power consumption of each channel is 150 mW from a 3.3 V supply.

High Gain CMOS Transimpedance Amplifier For Near Infrared Spectroscopy Applications

“…The small curren tconversion obtained by photodiode into voltage is the primary goal of TIA, during which it possibly adds as little noise to the output signal. Accordingly, the circuit is regarded as various properties, such as Transimpedance gain, group delay, and input referred noise current [14].As expressed by following equation, the ratio of output voltage to input current is considered as TIA Transimpedance gain…”

“…Through that, an output noise voltage same as the original noisy circuit can be produced.As defined by the subsequent equation , input referred noise currentis correlated to output noise voltage. The prevailing TIAcircuit diagram shown in Figure 2 consists of two phases, namely RGC input stage [14] and an inverter cascode based output stage [15].The bandwidth is increased through RGC low input impedance, whereas the Transimpedance gain is improved through inverter cascode stage (Mn1, Mn2, Mp1, Mp2) extreme open loop gain as well as huge output impedance. By eliminating the necessity of additional biasing source and PAD, the signal RAEEUCCI-2022 Journal of Physics: Conference Series 2335 (2022) 012039 from the regulating inverter amplifier of RGC biases the cascode transistor Mn2.…”

A 25 Gbps single‐end input limiting amplifier with loss of signal for low power integrated optical receivers

“…Dummy PD and differential TIA are employed to balance the capacitance loading of TIA input and attenuate common mode noise, but it has the disadvantages of more cost and power consumption. In order to realize low cost, one method is that the dummy PD is replaced with the internal capacitance in the chip, [3][4][5] and it needs differential TIA to generate differential output to the latter LA. Another method is that the dummy PD is removed, 6,7 so it also needs dummy TIA or differential TIA to generate DC point.…”