100GB/S two-iteration concatenated BCH decoder architecture for optical communications

Lee, Kihoon; Kang, Han-Gil; Park, Jeong-In; Lee, Hanho

doi:10.1109/sips.2010.5624879

Cited by 8 publications

(18 citation statements)

References 5 publications

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“…Interleaving not only leads to increased throughput, but also offers error correction advantages in certain types of channels (K. Lee et al 2010). This is because in many types of channels, errors tend to occur in bursts.…”

Section: Improving Throughputmentioning

confidence: 99%

Optimization of multi-channel BCH error decoding for common cases

Dill¹,

Shrivastava²,

Oh³

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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Error correcting systems have put increasing demands on system designers, both due to increasing error correcting requirements and higher throughput targets. These requirements have led to greater silicon area, power consumption and have forced system designers to make trade-offs in Error Correcting Code (ECC) functionality. Solutions to increase the efficiency of ECC systems are very important to system designers and have become a heavily researched area.Many such systems incorporate the Bose-Chaudhuri-Hocquenghem (BCH) method of error correcting in a multi-channel configuration. BCH is a commonly used code because of its configurability, low storage overhead, and low decoding requirements when compared to other codes. Multi-channel configurations are popular with system designers because they offer a straightforward way to increase bandwidth. The ECC hardware is duplicated for each channel and the throughput increases linearly with the number of channels. The combination of these two technologies provides a configurable and high throughput ECC architecture.This research proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. In this thesis, I examine how error frequency effects the utilization of BCH hardware. Rather than implement each decoder as a single pipeline of independent decoding stages, the channels are considered together and served by a pool of decoding stages. Modified hardware blocks for handling common cases are included and the pool is sized based on an acceptable, but negligible decrease in performance. i This thesis's experimental approach examines multi-channel configurations found in typical NAND flash systems. My experimental data shows that the proposed pooled group approach requires significantly fewer hardware blocks than a traditional multi-channel configuration. By allowing a 2% performance degradation and sizing the decoding pool appropriately, the scheme reduces hardware area by 47%-71% and dynamic power by 44%-59%.Additionally, I examined what improvements were possible with the improved design using the same hardware area as the traditional implementation. My experiments show that an improved throughput of 3x-5x can be achieved or NAND flash lifetime can be extended by 1.4x-4.5x. Dr. Shrivastava has provided invaluable input into both my research and my writing.

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Section: Improving Throughputmentioning

confidence: 99%

Optimization of multi-channel BCH error decoding for common cases

Dill¹,

Shrivastava²,

Oh³

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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“…Also, the L-CBCH code provides 8.91 dB NCG at 10 -15 decoder output BER with only two-iterative decoding. The L-CBCH decoder for 100 Gb/s OTN in [4] reduced hardware complexity approximately 34% with only 0.08 dB decrease in NCG performance compared to the I.3-CBCH code. However, the redundancy ratio of L-CBCH code is 6.81% because it uses fixed stuff (FS) byte in optical channel data unit (ODU) frame.…”

Section: Inmentioning

confidence: 99%

“…With the B-format OTN frame structure, two-parallel processing of encoding and decoding is possible. Detailed structure of A and B-format is described in [3][4]. After converted, each B-format frame is processed in the outer encoder and it aligned into 8 BCH(3920,3824) codewords, as shown in Fig.…”

Section: B Proposed Six-iteration Concatenated Bch Code Schemementioning

confidence: 99%

A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications

Lee

2010

2010 International SoC Design Conference

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Abstract-This paper presents a six-iteration concatenated BoseChaudhuri-Hocquenghem (BCH) code and its high-speed twoparallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed six-iteration concatenated BCH code structure with a block interleaving methods allows the decoder to achieve 9.19 dB net coding gain performance at 10 -15 decoder output bit error rate to compensate for serious transmission quality degradation. Also, the proposed high-speed concatenated BCH decoder architecture was implemented to support 100 Gb/s data processing rate. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s longhaul optical communications.

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“…Bose-Chaudhuri-Hocquenghem (BCH) codes are important multiple-error-correcting cyclic codes that are widely used in communications and storage systems [1,2]. The most widely used decoding method for BCH codes is the Berlekamp-Massey (BM) algorithm [2].…”

Section: Introductionmentioning

confidence: 99%

“…The most widely used decoding method for BCH codes is the Berlekamp-Massey (BM) algorithm [2]. The decoding procedure of the BM algorithm consists of the following three major steps: First, for a t-error-correcting BCH code and symbols from the Galois-field GF (2 m ), calculate 2t syndrome values S i (i=1, 2, ..., 2t) from the received codeword.…”

Section: Introductionmentioning

confidence: 99%

Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

Yeon¹,

Yang²,

Kim³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a low-complexity triple-error-correcting parallel Bose-ChaudhuriHocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-bystep (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multiparallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF(2 12 ), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

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100GB/S two-iteration concatenated BCH decoder architecture for optical communications

Cited by 8 publications

References 5 publications

Optimization of multi-channel BCH error decoding for common cases

Optimization of multi-channel BCH error decoding for common cases

A high-performance concatenated BCH code and its hardware architecture for 100 Gb/s long-haul optical communications

Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

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