Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

Yeon, Jae-Woong; Yang, Shaopeng; Kim, Cheol-Ho; Lee, Hanho

doi:10.5573/jsts.2013.13.5.465

Cited by 5 publications

(6 citation statements)

References 10 publications

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“…In Table 1 [ 7,8,10,14 ] , Dec 4 costs about 2.5 kbits of RAMs, while Dec 5 costs about 544 kbits of RAMs. For examples, the error pattern of the

(15, 7, 2)

code can be represented by the middle 8 syndrome bits (or middle 2 syndrome components

S_{2}

and

S_{3}

G F (2^{4})

), while the error pattern of the

(31, 16, 3)

can be represented by 15 syndrome bits (or just 3 syndrome components

S_{3}

S_{4}

and

S_{5}

G F (2^{5})

).…”

Section: The Bch (15 7 2) and (31 16 3) Decodermentioning

confidence: 99%

A Simple BCH Decoder for NoC Interconnects and SoC Buses

Wu¹,

Ailin²

2021

Chinese J of Electronics

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Network on a chip (NoC) uses packet‐switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on‐chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp's algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and control lines without storage.

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“…In Table 1 [ 7,8,10,14 ] , Dec 4 costs about 2.5 kbits of RAMs, while Dec 5 costs about 544 kbits of RAMs. For examples, the error pattern of the

(15, 7, 2)

code can be represented by the middle 8 syndrome bits (or middle 2 syndrome components

S_{2}

and

S_{3}

G F (2^{4})

), while the error pattern of the

(31, 16, 3)

can be represented by 15 syndrome bits (or just 3 syndrome components

S_{3}

S_{4}

and

S_{5}

G F (2^{5})

).…”

Section: The Bch (15 7 2) and (31 16 3) Decodermentioning

confidence: 99%

A Simple BCH Decoder for NoC Interconnects and SoC Buses

Wu¹,

Ailin²

2021

Chinese J of Electronics

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“…As mentioned, S i (i=1, 3) is required in m-SBS algorithm-based HD-BCH decoding [4] to calculate the syndrome. The SC consists of a parallel SC cell to receive the parallelized codeword, as shown in Fig.…”

Section: A Syndrome Calculatormentioning

confidence: 99%

“…The hard-decision kernel uses a HD-BCH decoding structure based on an m-SBS algorithm [4]. It consists of the SC block, the SFC block, and the CS and MC block, as shown in Fig.…”

Section: Hard-decision Kernelmentioning

confidence: 99%

“…Specifically, the SD-BCH decoder has test syndrome computation (TSC), which eliminates the test pattern generator, a hard-decision kernel based on a modified step-by-step (m-SBS) algorithm [4], and error location decision (ELD). Although the SD-BCH decoder generally uses an iteration method, the proposed SD-BCH decoder does not require iteration.…”

Section: Introductionmentioning

confidence: 99%

“…Bose-Chaudhuri-Hocquenghem (BCH) codes are important multiple-error-correcting cyclic codes that are widely used in communications and storage systems [2]- [4]. In the WBAN [1], the BCH (63, 51) code and its shortened (31, 19) code are adopted to enhance transmission reliability under different channel conditions.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

Jung¹,

Kim²,

Lee³

2016

JSTS:Journal of Semiconductor Technology and Science

Self Cite

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Abstract-This paper presents a low-complexity noniterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

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